ATMEGA165P-16MUR Atmel, ATMEGA165P-16MUR Datasheet - Page 136
![IC MCU AVR 16K 16MHZ 64MLF](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA165P-16MUR
Manufacturer Part Number
ATMEGA165P-16MUR
Description
IC MCU AVR 16K 16MHZ 64MLF
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165P-16MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8019K–AVR–11/10
PWM mode is shown in
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2A and TCNT2.
Figure 16-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.
Setting the COM2A[1:0] bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COM2A[1:0] to three (see
actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by setting (or clearing) the OC2A Register at the com-
pare match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the
timer clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM2A[1:0]
bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC2A to toggle its logical level on each compare match (COM2A[1:0] = 1). The waveform
generated will have a maximum frequency of f
ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
TCNTn
OCnx
OCnx
Period
1
Figure
2
16-6. The TCNT2 value is in the timing diagram shown as a his-
3
f
OCnxPWM
4
oc2
5
=
= f
----------------- -
N 256
f
clk_I/O
clk_I/O
⋅
6
/2 when OCR2A is set to zero. This fea-
7
Table 16-4 on page
ATmega165P
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
144). The
136
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