ATMEGA165P-16MUR Atmel, ATMEGA165P-16MUR Datasheet - Page 58
![IC MCU AVR 16K 16MHZ 64MLF](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA165P-16MUR
Manufacturer Part Number
ATMEGA165P-16MUR
Description
IC MCU AVR 16K 16MHZ 64MLF
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165P-16MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.2
11.2.1
11.2.2
8019K–AVR–11/10
Register Description
EICRA – External Interrupt Control Register A
EIMSK – External Interrupt Mask Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 11-1.
• Bit 7 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
• Bit 6 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-
rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
Bit
(0x69)
Read/Write
Initial Value
Bit
0x1D (0x3D)
Read/Write
Initial Value
ISC01
0
0
1
1
Interrupt 0 Sense Control
ISC00
PCIE1
R/W
R
7
–
0
7
0
0
1
0
1
PCIE0
Table
R/W
Description
The low level of INT0 generates an interrupt request
Any logical change on INT0 generates an interrupt request
The falling edge of INT0 generates an interrupt request
The rising edge of INT0 generates an interrupt request
R
6
–
0
6
0
11-1. The value on the INT0 pin is sampled before detecting
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
R
2
–
0
2
–
R
0
ISC01
ATmega165P
R/W
1
0
R
1
–
0
ISC00
R/W
INT0
R/W
0
0
0
0
EICRA
EIMSK
58
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