LPC1224FBD48/201 NXP Semiconductors, LPC1224FBD48/201 Datasheet - Page 20

• Manufacturer Part Number: LPC1224FBD48/201
• Description: MCU 32BIT 32K FLASH 4K 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of LPC1224FBD48/201

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 45MHz
• Connectivity: I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5153; LPC1224FBD48/201

NXP Semiconductors
LPC122X
Objective data sheet
7.10.1 Features
7.12.1 Features
7.11.1 Features
7.12 I
7.11 SSP/SPI serial I/O controller
The LPC122x contain one SSP/SPI controller. The SSP/SPI controller is capable of
operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
The LPC122x contain one I
The I
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
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C-bus serial I/O controller
16-byte Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Auto-baud capabilities and FIFO control mechanism that enables software flow
control implementation.
Support for RS-485/9-bit mode (UART0).
Support for modem control (UART0).
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
The I
supports I
Programmable digital glitch filter providing a 60 ns to 1 s input filter.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
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C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
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C-interface is a standard I
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C Fast-mode Plus with bit rates of up to 1 Mbit/s.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 29 March 2011
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C-bus controller.
2
C-compliant bus interface with open-drain pins and
32-bit ARM Cortex-M0 microcontroller
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C is a multi-master bus and can be
LPC122x
© NXP B.V. 2011. All rights reserved.
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