LPC1224FBD48/201 NXP Semiconductors, LPC1224FBD48/201 Datasheet - Page 3

• Manufacturer Part Number: LPC1224FBD48/201
• Description: MCU 32BIT 32K FLASH 4K 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of LPC1224FBD48/201

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 45MHz
• Connectivity: I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5153; LPC1224FBD48/201

NXP Semiconductors
3. Applications
LPC122X
Objective data sheet











Digital peripherals
Analog peripherals
Power
Unique device serial number for identification.
3.3 V power supply.
Available as 64-pin and 48-pin LQFP package.
eMetering
Lighting
Industrial networking
Alarm systems
White goods


















Micro DMA controller with 21 channels.
CRC engine.
Two UARTs with fractional baud rate generation and internal FIFO. One UART with
RS-485 and modem support and one standard UART with IrDA.
SSP/SPI controller with FIFO and multi-protocol capabilities.
I
data rate of 1 Mbit/s with multiple address recognition and monitor mode. I
pins have programmable glitch filter.
Up to 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor,
open-drain mode, programmable digital input glitch filter, and programmable input
inverter.
Programmable output drive on all GPIO pins. Four pins support high-current output
drivers.
All GPIO pins can be used as edge and level sensitive interrupt sources.
Four general purpose counter/timers with four capture inputs and four match
outputs (32-bit timers) or two capture inputs and two match outputs (16-bit timers).
Windowed WatchDog Timer (WWDT).
One 8-channel, 10-bit ADC.
Two highly flexible analog comparators. Comparator outputs can be programmed
to trigger a timer match signal or can be used to emulate 555 timer behavior.
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Processor wake-up from Deep-sleep mode via start logic using 12 port pins.
Processor wake-up from Deep-power down and Deep-sleep modes via the RTC.
Brownout detect with three separate thresholds each for interrupt and forced reset.
Power-On Reset (POR).
Integrated PMU (Power Management Unit).
2
C-bus interface supporting full I
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 29 March 2011
2
C-bus specification and Fast-mode Plus with a
32-bit ARM Cortex-M0 microcontroller
LPC122x
© NXP B.V. 2011. All rights reserved.
2
C-bus
3 of 60