NUC100RE3AN Nuvoton Technology Corporation of America, NUC100RE3AN Datasheet - Page 131
![IC MCU 32BIT 128KB FLASH 64LQFP](/photos/28/73/287358/nuc100re3an_sml.jpg)
NUC100RE3AN
Manufacturer Part Number
NUC100RE3AN
Description
IC MCU 32BIT 128KB FLASH 64LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC100RE3AN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
49
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
NUC100RE3AN
Manufacturer:
NuvoTon
Quantity:
2 000
Company:
Part Number:
NUC100RE3AN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
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Part Number:
NUC100RE3AN
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NUVOTON
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Power-On-Reset Control Register (PORCR)
Register
PORCR
Bits
[31:16]
[15:0]
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
POR_DIS_CODE
Offset
GCR_BA+0x24
30
22
14
6
R/W
R/W
Reserved
The register is used for the Power-On-Reset enable control (write-protection bits)
When power on, the POR circuit generates a reset signal to reset the whole chip
function, but noise on the power may cause the POR active again. User can disable
internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5
to this field.
The POR function will be active again when this field is set to another value or chip is
reset by other reset source, including:
/RESET, Watch dog, LVR reset, BOD reset, ICE reset command and the software-chip
reset function
This bit is the protected bit. It means programming this needs to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100.
29
21
13
5
Description
Power-On-Reset Controller Register
POR_DIS_CODE[15:8]
POR_DIS_CODE[7:0]
28
20
12
4
- 131 -
Reserved
Reserved
27
19
11
3
Publication Release Date: Oct 22, 2010
26
18
10
2
25
17
9
1
Revision V1.06
Reset Value
0x0000_00XX
24
16
8
0
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