NUC100RE3AN Nuvoton Technology Corporation of America, NUC100RE3AN Datasheet - Page 16
![IC MCU 32BIT 128KB FLASH 64LQFP](/photos/28/73/287358/nuc100re3an_sml.jpg)
NUC100RE3AN
Manufacturer Part Number
NUC100RE3AN
Description
IC MCU 32BIT 128KB FLASH 64LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC100RE3AN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
49
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC100RE3AN
Manufacturer:
NuvoTon
Quantity:
2 000
Company:
Part Number:
NUC100RE3AN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC100RE3AN
Manufacturer:
NUVOTON
Quantity:
20 000
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• I
• I
• PS2 Device Controller
• EBI (External bus interface) support (Low Density 64-pin Package Only)
• ADC
• Analog Comparator
• One built-in temperature sensor with 1℃ resolution
• Brown-out detector
2
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Up to two sets of I2C device
Master/Slave up to 1Mbit/s
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Programmable clocks allow versatile rate control
Support multiple address recognition (four slave address with mask option)
Interface with external audio CODEC
Operate as either master or slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Mono and stereo audio data supported
I
Two 8 word FIFO data buffers are provided, one for transmit and one for receive
Generates interrupt requests when buffer levels cross a programmable boundary
Support two DMA requests, one for transmit and one for receive
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
S/W override bus
Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode
Support 8bit/16bit data width
Support byte write in 16bit data width mode
12-bit SAR ADC with 600K SPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion start by software programming or external input
Support PDMA mode
Up to two analog comparator
External input or internal bandgap voltage selectable at negative node
Interrupt when compare result change
Power down wake up
With 4 levels: 4.5V/3.8V/2.7V/2.2V
NuMicro™ NUC100 Series Technical Reference Manual
2
S and MSB justified data format supported
- 16 -
Publication Release Date: Dec. 22, 2010
Revision V1.06
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