NUC100RE3AN Nuvoton Technology Corporation of America, NUC100RE3AN Datasheet - Page 300
![IC MCU 32BIT 128KB FLASH 64LQFP](/photos/28/73/287358/nuc100re3an_sml.jpg)
NUC100RE3AN
Manufacturer Part Number
NUC100RE3AN
Description
IC MCU 32BIT 128KB FLASH 64LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC100RE3AN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
49
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC100RE3AN
Manufacturer:
NuvoTon
Quantity:
2 000
Company:
Part Number:
NUC100RE3AN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC100RE3AN
Manufacturer:
NUVOTON
Quantity:
20 000
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PWM Clock Selector Register (CSR)
Register
CSR
Bits
[31:15]
[14:12]
[11]
[10:8]
[7]
[6:4]
Reserved
Reserved
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
PWMA_BA+0x04 R/W
PWMB_BA+0x04 R/W
Descriptions
Reserved
CSR3
Reserved
CSR2
Reserved
CSR1
30
22
14
6
R/W
CSR3
CSR1
Reserved
PWM Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7
for group B)
Select clock input for PWM timer.
Reserved
PWM Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6
for group B)
Select clock input for PWM timer.
(Table is the same as CSR3)
Reserved
PWM Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5
for group B)
Select clock input for PWM timer.
(Table is the same as CSR3)
29
21
13
CSR3 [14:12]
100
011
010
001
000
5
Description
PWM Group A Clock Selector Register
PWM Group B Clock Selector Register
(Medium Density Only)
28
20
12
4
- 300 -
Reserved
Reserved
Reserved
Reserved
Input clock divided by
1
16
8
4
2
27
19
11
3
Publication Release Date: Dec. 22, 2010
26
18
10
2
CSR2
CSR0
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
0x0000_0000
24
16
8
0
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