MC9S08SH8CWJR Freescale Semiconductor, MC9S08SH8CWJR Datasheet - Page 82
MC9S08SH8CWJR
Manufacturer Part Number
MC9S08SH8CWJR
Description
IC MCU 8BIT 8K FLASH 20WSOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH8CWJR.pdf
(338 pages)
Specifications of MC9S08SH8CWJR
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Interface Type
SPI, SCI, RS-232
Maximum Clock Frequency
5 MHz, 40 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Chapter 6 Parallel Input/Output Control
6.6.1.4
6.6.1.5
82
PTASE[4:0]
PTADS[4:0]
Reserved
Reserved
Reset:
Reset:
Field
Field
4:0
4:0
5
5
W
W
R
R
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
Port A Slew Rate Enable Register (PTASE)
0
0
Port A Drive Strength Selection Register (PTADS)
0
0
7
7
Figure 6-7. Drive Strength Selection for Port A Register (PTADS)
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
0
0
0
0
6
6
Table 6-5. PTASE Register Field Descriptions
Table 6-6. PTADS Register Field Descriptions
MC9S08SH8 MCU Series Data Sheet, Rev. 3
R
R
0
0
5
5
PTADS4
PTASE4
0
0
4
4
Description
Description
PTADS3
PTASE3
3
0
3
0
PTASE2
PTADS2
0
0
2
2
PTASE1
PTADS1
Freescale Semiconductor
0
0
1
1
PTASE0
PTADS0
0
0
0
0
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