PK30N512VLK100 Freescale Semiconductor, PK30N512VLK100 Datasheet

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... Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © 2010–2011 Freescale Semiconductor, Inc. Preliminary Document Number: K30P81M100SF2 Rev. 4, 3/2011 K30P81M100SF2 • ...

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... I2S switching specifications..................................50 6.9 Human-machine interfaces (HMI)......................................52 6.9.1 TSI electrical specifications...................................52 6.9.2 LCD electrical characteristics................................53 7 Dimensions...............................................................................54 7.1 Obtaining package dimensions.........................................54 8 Pinout........................................................................................54 8.1 K30 Signal Multiplexing and Pin Assignments..................54 8.2 K30 Pinouts.......................................................................58 9 Revision History........................................................................60 Preliminary Freescale Semiconductor, Inc. ...

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... Field Q Qualification status K## Kinetis family M Flash memory type K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. http://www.freescale.com Description • Fully qualified, general market flow • Prequalification • K30 • Program flash only • Program flash and FlexMemory Table continues on the next page ...

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... MC = 121 MAPBGA ( mm) • 144 LQFP ( mm) • 144 MAPBGA ( mm) • 196 MAPBGA ( mm) • 256 MAPBGA ( mm) • MHz • MHz • 100 = 100 MHz • 120 = 120 MHz • 150 = 150 MHz • Tape and reel • (Blank) = Trays Preliminary Values Freescale Semiconductor, Inc. ...

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... Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. Max. 0.9 1.1 Min. Max. 10 130 Min. ...

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... Result of exceeding a rating Measured characteristic K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 6 Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Preliminary Max. Unit V Freescale Semiconductor, Inc. ...

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... Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Normal Limited operating operating range ...

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... Ambient temperature A V 3.3 V supply voltage DD 4 Ratings K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 8 Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Preliminary Max. Unit 130 µ 150 °C 105 °C 25 °C –40 °C Unit °C V Freescale Semiconductor, Inc. ...

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... Description V Digital supply voltage DD I Digital supply current DD V Digital input voltage (except RESET, EXTAL, and XTAL) DIO K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. –55 — — Min. — Min. -2000 -500 -100 Table continues on the next page... ...

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... V — DD — 0.75 × — 0.35 × — 0.3 × 0.06 × V — –0.2 0 –5 1.2 — TBD — Preliminary Max. Unit 3.8 V Unit Notes Freescale Semiconductor, Inc. ...

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... Table 3. VBAT power operating requirements Symbol Description V Falling VBAT supply POR detect voltage POR_VBAT K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. , and induce an injection current when V SS supply LVD and POR operating requirements Min. TBD TBD TBD ...

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... OL — — — min and Vinput = min and Vinput = and VLLSx→RUN recovery times in the following table Preliminary Max. Unit Notes — V — V — V — V 100 mA 0.5 V 0.5 V 0.5 V 0.5 V 100 mA 1 μ μA 50 kΩ kΩ 3 Freescale Semiconductor, Inc. ...

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... I Analog supply current DDA I Run mode current — all peripheral clocks DD_RUN disabled, code executing from flash • @ 1.8V • @ 3.0V K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. — DD — — — — — — — ...

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... TBD — 35 TBD — 15 TBD — 0.4 TBD — 1.25 TBD — TBD TBD — 1.05 TBD — 50 TBD — 12 TBD — 8 TBD — 4 TBD — 2 TBD — 550 TBD Preliminary Unit Notes μA μA μA μA μ Freescale Semiconductor, Inc. ...

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... MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) • All peripheral clocks enabled but peripherals are not in active operation • LVD disabled • No GPIOs toggled • Code execution from flash K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary General 15 ...

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... MHz (crystal OSC K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 16 Frequency Typ. band (MHz) 0.15–50 TBD 50–150 TBD 150–500 TBD 500–1000 TBD 0.15–1000 TBD = 96 MHz SYS Preliminary Unit Notes dBμ — Freescale Semiconductor, Inc. ...

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... Flash clock FLASH f System and core clock SYS f Bus clock BUS f Flash clock FLASH K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Table 8. Capacitance attributes Min. Normal run mode — — — VLPR mode — — — Preliminary General Min ...

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... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 18 Min. Max. 1.5 — 100 — 16 — TBD — 2 — — 12 — 36 — 32 — 36 Min. –40 –40 Preliminary Unit Notes Bus clock 1 cycles Bus clock cycles Max. Unit 125 °C 105 °C Freescale Semiconductor, Inc. ...

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... Debug trace timing specifications Table 10. Debug trace operating behaviors Symbol Description T Clock period cyc T Low pulse width wl K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 81 MAPBGA TBD TBD TBD TBD TBD TBD TBD Frequency dependent Table continues on the next page ...

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... JTAG and CJTAG • Serial Wire Debug J2 TCLK cycle period K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 Table continues on the next page... Preliminary Min. Max. Unit 2 — ns — — — — Min. Max. Unit 2.7 3.6 V MHz 1/J1 — ns Freescale Semiconductor, Inc. ...

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... TCLK low to boundary scan output data valid J8 TCLK low to boundary scan output high-Z J9 TMS, TDI input data setup time to TCLK rise K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table continues on the next page... Preliminary Min. Max. ...

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... Figure 6. Boundary scan (JTAG) timing K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 Figure 5. Test clock input timing Preliminary Min. Max. Unit 1.4 — ns — 22.1 ns — 22.1 ns 100 — — Input data valid Output data valid Output data valid Freescale Semiconductor, Inc. ...

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... J13 TRST 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J11 J12 J11 Figure 7. Test Access Port timing J14 Figure 8 ...

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... TBD %f dco — 4 MHz — 5 MHz — µA TBD µs — — kHz — — kHz — 39.0625 kHz 25 MHz 2, 50 MHz 75 MHz 100 MHz Freescale Semiconductor, Inc ...

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... This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE crystal/resonator is being used as the reference, this specification assumes it is already running. K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — ...

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... Table continues on the next page... Preliminary Max. Unit Notes 3 — nA — μA — μA — μA — mA — — μA — μA — μA — mA — mA — mA — — — MΩ — MΩ — MΩ — MΩ Freescale Semiconductor, Inc. ...

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... Input clock frequency (external clock mode) ec_extal t Input clock duty cycle (external clock mode) dc_extal K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — — — — ...

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... Min. Typ. 1.71 — — 100 — 2.5 — 15 — 0.6 Min. Typ. Max. — 32 — — 1000 — Preliminary Unit Notes Max. Unit 3.6 V — MΩ — pF — pF — V Unit Notes kHz ms 1 Freescale Semiconductor, Inc. ...

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... Read 1s All Blocks execution time rd1all t Read Once execution time rdonce t Program Once execution time pgmonce K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 20 — 20 — 160 Min. Typ. ...

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... Table continues on the next page... Preliminary Max. Unit Notes 1600 μs 1 Typ. Unit 10 mA Max. Unit Notes 1 — years 2 — years 2 — years 2 — cycles 3 Min. Max. Unit 2.7 3.6 V — MHz SYS — MHz SYS — ns EZP_CK 5 — — ns Freescale Semiconductor, Inc. ...

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... Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DP3. K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EP3 EP2 EP4 EP9 EP7 ...

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... Table continues on the next page... Preliminary Table 25 and Max. Unit Notes 3.6 V +100 mV 2 +100 DDA V V SSA V V REFH kΩ kΩ 4 18.0 MHz 5 12.0 MHz 6 818.330 Ksps Freescale Semiconductor, Inc. ...

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... For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp Figure 10. ADC input impedance equivalency diagram K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1 Max. Typ. 37.037 — 361.402 = 1.0 MHz unless otherwise stated. Typical values are for ADCK SIMPLIFIED ...

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... MHz ±TBD ADC 4 LSB conversion ±1 clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) ±TBD 4 ADC LSB conversion ±0.5 clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) ±TBD Max 4 LSB averaging ±TBD ±TBD LSB ADIN V ±TBD DDA — 4 LSB ±0.5 Freescale Semiconductor, Inc. ...

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... )/2 REFH REFL 5. Input data is 1 kHz sine wave. FIGURE TBD Figure 11. Typical TUE vs. ADC conversion rate 12-bit single-ended mode K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = REFH DDA REFL 1 Min. Typ. ...

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... Min. Typ. — 590 — TBD Table continues on the next page... Preliminary Max. Unit Notes 3 DDA V V DDA — kΩ 4 IN+ to IN- — — — Ω 5 — µs 6 causes drop AS 1 Max. Unit Notes TBD μ TBD μA 3 Freescale Semiconductor, Inc. ...

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... V Maximum PP,DIFF differential input signal swing SNR Signal-to-noise • Gain=1 ratio • Gain=64 K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. TBD 0.98 TBD 1.99 TBD 3.97 TBD 7.95 TBD 15 ...

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... Average=32, f =500Hz in — bits 16-bit differential — bits mode, — bits f =500Hz in — bits — bits — bits — bits — bits — bits — bits — bits dB Typ. Max. Unit — 3.6 V — 200 μA Freescale Semiconductor, Inc. ...

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... Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level LSB = V /64 reference K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — V – 0.3 SS — ...

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... Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 1.3 1.6 1.9 2.2 Vin level (V) Preliminary HYSTCTR S etting 2.5 2.8 3.1 Freescale Semiconductor, Inc. ...

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... The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO small load capacitance (47 pF) can improve the bandwidth performance of the DAC K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1 ...

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... TBD DACR ±8 LSB 2 ±1 LSB 3 ±1 LSB 4 ±0.8 %FSR 5 ±0.6 %FSR — μV/C — ppm of FSR/C TBD μV/yr 250 Ω V/μs — — -80 dB kHz — — Freescale Semiconductor, Inc. ...

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... Calculated by a best fit curve from V Figure 15. Typical INL error vs. digital code K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors +100 mV to VREF−100 mV SS Preliminary 43 ...

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... V and temperature=25C DDA K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 44 Min. 1.71 −40 — Min. Typ. TBD 1.2 Table continues on the next page... Preliminary Max. Unit Notes 3.6 V 105 °C 100 nF Max. Unit Notes TBD V Freescale Semiconductor, Inc. ...

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... TBD Figure 17. Typical output vs.temperature TBD 6.7 Timers See General switching specifications. 6.8 Communication interfaces K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. TBD 1.198 — — — — — — ...

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... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 46 Min. 1.71 — BCLK (t / SCK (t / SCK (t / SCK — DS1 DS2 DS8 Data Last data First data DS5 DS6 First data Data Last data Preliminary Max. Unit Notes 3 12.5 MHz — SCK/2) — ns — — ns — ns — ns DS4 Freescale Semiconductor, Inc. ...

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... Table 36. Master mode DSPI timing (high-speed mode) Num Operating voltage Frequency of operation K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Description DS10 DS15 DS12 First data ...

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... SCK (t /2) − 2 — ns SCK (t /2) − 2 — ns SCK — 8.5 ns −2 — ns TBD — — ns DS4 Min. Max. Unit 2.7 3.6 V 12.5 MHz — ns BCLK (t /2) − SCK SCK — TBD ns 0 — — — ns — — Freescale Semiconductor, Inc. ...

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... Clock low time WL SD3 t Clock high time WH SD4 t Clock rise time TLH K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DS10 DS15 DS12 First data Data DS14 First data Data Card input clock Table continues on the next page ...

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... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 50 (continued) SD3 SD2 SD1 SD6 SD7 SD8 Figure 23. SDHC timing master (clocks driven) and slave 2 S master mode timing Table continues on the next page... Preliminary Min. Max. Unit — 6 — — ns Min. Max. Unit 2.7 3 SYS Freescale Semiconductor, Inc. ...

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... I2S_FS input hold after I2S_BCLK S15 I2S_BCLK to I2S_TXD/I2S_FS output valid S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid S17 I2S_RXD setup before I2S_BCLK K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2 S master mode timing (continued ...

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... TBD — TBD — TBD Table continues on the next page... Preliminary Min. Max. Unit 2 — ns S16 S14 S16 Max. Unit Notes 3.6 V 500 pF 1 TBD MHz TBD MHz TBD pF TBD mV TBD μA 2 TBD μA 2 TBD % 3 TBD % 4 TBD % 5 Freescale Semiconductor, Inc. ...

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... HREFSEL = current adder — RVEN = 1 VIREG IREG I RBIAS current adder RBIAS • HREFSEL = 0 • HREFSEL = 1 K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 0.003 0.25 0.003 — — — — ...

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... V DD http://www.freescale.com and perform a keyword Then use this document number 98ASS23174W 98ASA10631D Preliminary Max. Unit Notes — MΩ — MΩ — V — V — V — V Freescale Semiconductor, Inc. ...

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... VDDA VDDA VDDA • 18 VREFH VREFH VREFH • 19 VREFL VREFL VREFL K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. NOTE ALT1 ALT2 ALT3 ALT4 PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 PTE1 SPI1_SOUT UART1_RX SDHC0_D0 PTE2 SPI1_SCK UART1_CT SDHC0_DC S_b ...

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... FTM0_FLT2 FTM_CLKIN 0 PTA19 FTM1_FLT0 FTM_CLKIN 1 Preliminary ALT5 ALT6 ALT7 EzPort JTAG_TCL EZP_CLK K/ SWD_CLK JTAG_TDI EZP_DI JTAG_TDO/ EZP_DO TRACE_SW O JTAG_TMS/ SWD_DIO NMI_b EZP_CS_b CMP2_OUT I2S0_RX_B JTAG_TRS CLK T I2S0_TXD FTM1_QD_ PHA I2S0_TX_F FTM1_QD_ S PHB I2S0_TX_B CLK I2S0_RXD I2S0_RX_F S I2S0_MCLK I2S0_CLKIN LPT0_ALT1 Freescale Semiconductor, Inc. ...

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... PTC3 LCD_P23/ LCD_P23/ CMP1_IN1 CMP1_IN1 • 59 VSS VSS VSS • 60 VLL3 VLL3 VLL3 K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTB0 I2C0_SCL FTM1_CH0 PTB1 I2C0_SDA FTM1_CH1 PTB2 I2C0_SCL UART0_RT S_b PTB3 I2C0_SDA UART0_CT ...

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... FTM0_CH5 S_b PTD6 SPI0_PCS3 UART0_RX FTM0_CH6 PTD7 CMT_IRO UART0_TX FTM0_CH7 Preliminary ALT5 ALT6 ALT7 EzPort CMP1_OUT LCD_P24 CMP0_OUT LCD_P25 LCD_P26 LCD_P27 LCD_P28 FTM2_FLT0 LCD_P29 LCD_P30 LCD_P31 LCD_P40 LCD_P41 LCD_P42 LCD_P43 EWM_IN LCD_P44 EWM_OUT LCD_P45 _b FTM0_FLT0 LCD_P46 FTM0_FLT1 LCD_P47 Freescale Semiconductor, Inc. ...

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... The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. The 81 MAPBGA ballmap assignments are currently being developed. K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. NOTE Preliminary Pinout 59 ...

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... The following table provides a revision history for this document. K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 60 Figure 26. K30 80 LQFP Pinout Diagram Preliminary 60 VLL3NC 59 VSS 58 PTC3 57 PTC2 56 PTC1 55 PTC0 54 PTB19 53 PTB18 52 PTB17 51 PTB16 50 PTB11 49 PTB10 48 PTB9 47 PTB8 46 PTB3 45 PTB2 44 PTB1 43 PTB0 42 RESET_b 41 PTA19 Freescale Semiconductor, Inc. ...

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... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Table 43. Revision History Substantial Changes Initial public revision Many updates throughout Corrected 81- and 104-pin package codes Added sections that were inadvertently removed in previous revision Reworded I footnote in "Voltage and Current Operating Requirements" ...

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... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time ...