PK40N512VMD100 Freescale Semiconductor, PK40N512VMD100 Datasheet - Page 33

• Manufacturer Part Number: PK40N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.4.1.3 Flash (FTFL) current and power specfications
6.4.1.4 Reliability specifications
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
2. Data retention is based on T
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ T
6.4.2 EzPort Switching Specifications
Freescale Semiconductor, Inc.
t
t
t
nvmretp10k
nvmretp100
n
Symbol
nvmretp1k
nvmcycp
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
EP1a
Num
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
I
Symbol
DD_PGM
Data retention after up to 10 K cycles
Data retention after up to 1 K cycles
Data retention after up to 100 cycles
Cycling endurance
Description
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
Worst case programming current in program flash
Description
Table 22. Flash (FTFL) current and power specfications
K40 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
javg
Table 24. EzPort switching specifications
Table 23. NVM reliability specifications
= 55°C (temperature profile over the lifetime of the application).
Program Flash
Preliminary
10 K
Min.
10
15
5
Peripheral operating requirements and behaviors
Typ.
j
TBD
TBD
TBD
TBD
≤ 125°C.
2 x t
1
1.71
Min.
—
—
EZP_CK
—
—
5
5
2
5
0
Max.
Typ.
10
—
—
—
—
f
f
Max.
SYS
SYS
3.6
12
12
—
—
—
—
—
—
/2
/8
cycles
years
years
years
Unit
Unit
mA
MHz
MHz
Unit
Notes
ns
ns
ns
ns
ns
ns
ns
ns
V
2
2
2
3
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