PK60X256VMD100 Freescale Semiconductor, PK60X256VMD100 Datasheet - Page 45

• Manufacturer Part Number: PK60X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK60X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 100
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.6.1.2 16-bit ADC electrical characteristics
Freescale Semiconductor, Inc.
I
Symbol
DDA_ADC
f
ENOB
ADACK
TUE
DNL
INL
E
E
FS
Q
Table 28. 16-bit ADC characteristics (V
Supply current
ADC
asynchronous
clock source
Sample Time
Total unadjusted
error
Differential non-
linearity
Integral non-
linearity
Full-scale error
Quantization
error
Effective number
of bits
Description
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
See Reference Manual chapter for sample times
16 bit differential mode
16 bit single-ended mode
Conditions
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
• ≤13 bit modes
• <12 bit modes
• ≤13 bit modes
• <12 bit modes
• ≤13 bit modes
• <12 bit modes
• ≤13 bit modes
• <12 bit modes
• 16 bit modes
• ≤13 bit modes
• Avg=32
• Avg=1
• Avg=32
• Avg=1
1
Table continues on the next page...
Preliminary
0.215
TBD
TBD
TBD
TBD
Min.
1.2
3.0
2.4
4.4
—
—
—
—
—
—
REFH
Peripheral operating requirements and behaviors
= V
-1 to 0
Typ.
±0.8
±0.5
±0.7
±0.2
±1.0
±0.5
±0.4
±1.0
13.6
13.2
TBD
TBD
DDA
2.4
4.0
5.2
6.2
—
—
2
, V
REFL
±TBD
±TBD
±TBD
±TBD
±TBD
±TBD
Max.
±0.5
±0.5
1.7
3.9
7.3
6.1
9.5
±1
—
—
—
—
—
= V
SSA
)
LSB
LSB
LSB
LSB
LSB
MHz
MHz
MHz
MHz
Unit
bits
bits
bits
bits
mA
4
4
4
4
4
t
conversion
%1, AVGS
conversion
%1, AVGS
averaging
averaging
averaging
ADACK
hardware
hardware
<12MHz,
(AVGE =
<12MHz,
(AVGE =
V
= %11)
= %11)
f
Notes
ADACK
clock
clock
V
ADC
ADC
Max
Max
Max
ADIN
DDA
3
5
= 1/
=
45