UJA1078ATW/3V3,112 NXP Semiconductors, UJA1078ATW/3V3,112 Datasheet - Page 26

• Manufacturer Part Number: UJA1078ATW/3V3,112
• Description: IC SBC CAN/LIN 3.3V HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1078ATW/3V3,112

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 84µA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1078A
Product data sheet
6.8.2.1 General fail-safe features
6.8.2.2 TXDL dominant time-out function
6.8.2 Fail-safe features
6.9 Local wake-up input
The following fail-safe features have been implemented:
A TXDL dominant time-out timer circuit prevents the bus lines being driven to a permanent
dominant state (blocking all network communications) if TXDL1 or TXDL2 is forced
permanently LOW by a hardware and/or software application failure. The timer is
triggered by a negative edge on the TXDL pin. If the pin remains LOW for longer than the
TXDL dominant time-out time (t
lines to a recessive state. The timer is reset by a positive edge on the TXDL pin.
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity
(falling, rising or both) of the wake-up pins can be configured independently via the WIC1
and WIC2 bits in the Int_Control register
wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either
of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal
mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and
enter Standby mode. The status of the wake-up pins can be read via the wake-up level
status bits (WLS1 and WLS2) in the WD_and_Status register
Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts
is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).
Fig 13. Wake-up pin sampling synchronized with WBIAS signal
•
•
•
Pins TXDL1 and TXDL2 have internal pull-ups towards V
states if these pins are left floating
The current of the transmitter output stage is limited in order to protect the transmitter
against short circuits to pin BAT
A loss of power (pins BAT and GND) has no impact on the bus lines or on the
microcontroller. There will be no reverse currents from the bus.
Wake-up int
WAKEx pin
WBIAS pin
WBIASI
(internal)
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 January 2011
enable bias
to(dom)TXDL
High-speed CAN/dual LIN core system basis chip
Table
), the transmitter is disabled, driving the bus
6). These bits can also be used to disable
disable bias
disable bias
wake level latched
V1
(Table
to guarantee safe, defined
UJA1078A
4).
© NXP B.V. 2011. All rights reserved.
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