UJA1078ATW/3V3,112 NXP Semiconductors, UJA1078ATW/3V3,112 Datasheet - Page 44

• Manufacturer Part Number: UJA1078ATW/3V3,112
• Description: IC SBC CAN/LIN 3.3V HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1078ATW/3V3,112

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 84µA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
[5]
[6]
[7]
UJA1078A
Product data sheet
A system reset will be performed if the watchdog is in Window mode and is triggered less than t
period (or in the first half of the watchdog period).
The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see
Window mode only.
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
Fig 17. Timing test circuit for CAN transceiver
Fig 18. CAN transceiver timing diagram
TXDC
CANH
CANL
V
RXDC
t
t
d(TXDCL-RXDCL)
O(dif)bus
d(TXDC-busdom)
C RXDC
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 January 2011
RXDC
TXDC
SBC
GND
BAT
t
d(busdom-RXDC)
High-speed CAN/dual LIN core system basis chip
t
d(TXDCH-RXDCH)
CANH
CANL
t
trig(wd)1
d(TXDC-busrec)
, but not more than t
R CANH − R CANL
trig(wd)1
015aaa079
trig(wd)2
after the start of the watchdog
C CANH − C CANL
0.9 V
0.5 V
UJA1078A
Table
, after the start of the
© NXP B.V. 2011. All rights reserved.
t
d(busrec-RXDC)
4); valid in watchdog
HIGH
LOW
dominant
recessive
HIGH
LOW
015aaa151
44 of 54