SCAN921023SLCX National Semiconductor, SCAN921023SLCX Datasheet
SCAN921023SLCX
Specifications of SCAN921023SLCX
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SCAN921023SLCX Summary of contents
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... Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to Block Diagrams © 2004 National Semiconductor Corporation use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the em- bedded clock guarantees a transition on the bus every 12-bit cycle ...
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Block Diagrams (Continued) Functional Description The SCAN921023 and SCAN921224 are a 10-bit Serializer and Deserializer chipset designed to transmit data over dif- ferential backplanes at clock speeds from MHz. The chipset is also capable of driving data ...
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Initialization (Continued) from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after both SYNC inputs return low. When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded ...
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TRI-STATE (Continued) TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, ...
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Ordering Information (Continued) DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DIN8 Held Low-DIN9 Held High Creates an RMT Pattern FIGURE 1. RMT Patterns Seen on the Bus LVDS Serial ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS/LVTTL Input Voltage −0. LVCMOS/LVTTL Output Voltage −0. Bus LVDS Receiver Input Voltage Bus LVDS Driver Output Voltage Bus LVDS Output Short ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter I Power-Off Output Current OX DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−) VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage ...
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Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Deterministic Jitter DJIT t Random Jitter RJIT Deserializer Timing Requirements for REFCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Deserializer PLL Lock Figure 15 DSR1 Time from PWRDWN Figure 16 (with SYNCPAT) (Note 7) t Deserializer PLL Lock DSR2 time from SYNCPAT t ...
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AC Timing Diagrams and Test Circuits FIGURE 2. “Worst Case” Serializer ICC Test Pattern FIGURE 3. “Worst Case” Deserializer ICC Test Pattern FIGURE 4. Serializer Bus LVDS Output Load and Transition Times FIGURE 5. Deserializer CMOS/TTL Output Load and Transition ...
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AC Timing Diagrams and Test Circuits FIGURE 6. Serializer Input Clock Transition Time Timing shown for TCLK_R/F = LOW FIGURE 8. Serializer TRI-STATE Test Circuit and Timing (Continued) FIGURE 7. Serializer Setup/Hold Times 11 20000107 20000108 20000109 www.national.com ...
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AC Timing Diagrams and Test Circuits FIGURE 9. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays www.national.com (Continued) FIGURE 10. SYNC Timing Delays FIGURE 11. Serializer Delay 12 20000110 20000123 20000111 ...
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AC Timing Diagrams and Test Circuits Timing shown for RCLK_R/F = LOW Duty Cycle ( RDC FIGURE 14. Deserializer TRI-STATE Test Circuit and Timing (Continued) FIGURE 12. Deserializer Delay FIGURE 13. Deserializer Data Valid Out Times 13 20000112 ...
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AC Timing Diagrams and Test Circuits FIGURE 15. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays FIGURE 16. Deserializer PLL Lock Time from SyncPAT www.national.com (Continued) 14 20000115 20000122 ...
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AC Timing Diagrams and Test Circuits SW - Setup and Hold Time (Internal Data Sampling Window Serializer Output Bit Position Jitter that results from Jitter on TCLK DJIT t = Receiver Noise Margin Time RNM FIGURE 17. Receiver ...
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Application Information USING THE SCAN921023 AND SCAN921224 The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of parallel LVTTL data over a serial Bus LVDS link up to 660 Mbps. An ...
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Application Information USING T AND T TO VALIDATE SIGNAL DJIT RNM QUALITY The parameters t and t can be used to generate an DJIT RNM eye pattern mask to validate signal quality in an actual application or in simulation. The ...
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Application Information Pin Diagrams www.national.com (Continued) FIGURE 21. Random Lock Hot Insertion SCAN921023SLC - Serializer (Top View) 18 20000117 20000130 ...
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Pin Diagrams (Continued) SCAN921224SLC - Deserializer (Top View) 19 20000131 www.national.com ...
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Serializer Pin Description Pin Name I/O DIN I TCLKR/F I DO+ O DO− O DEN I PWRDN I TCLK I SYNC I DVCC I DGND I AVCC I AGND I TDI I TDO O TMS I TCK I TRST I ...
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Deserializer Pin Description Pin Name I/O RCLK O REN I DVCC I DGND I AVCC I AGND I REFCLK I TDI I TDO O TMS I TCK I TRST I N/C N/A Deserializer Truth Table INPUTS PWRDN H (4) H ...
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... BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. ...