SCAN921023SLCX National Semiconductor, SCAN921023SLCX Datasheet - Page 3

• Manufacturer Part Number: SCAN921023SLCX
• Description: IC SERIALIZER 10BIT 49-FBGA
• Manufacturer: National Semiconductor
• Series: SCANr

Specifications of SCAN921023SLCX

• Function: Serializer
• Data Rate: 660Mbps
• Input Type: LVDS
• Output Type: LVDS
• Number Of Inputs: 10
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 49-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Initialization
from the LOCK pin. Under all circumstances, the Serializer
stops sending SYNC patterns after both SYNC inputs return
low.
When the Deserializer detects edge transitions at the Bus
LVDS input, it will attempt to lock to the embedded clock
information. When the Deserializer locks to the Bus LVDS
clock, the LOCK output will go low. When LOCK is low, the
Deserializer outputs represent incoming Bus LVDS data.
Data Transfer
After initialization, the Serializer will accept data from inputs
DIN0–DIN9. The Serializer uses the TCLK input to latch
incoming Data. The TCLK_R/F pin selects which edge the
Serializer uses to strobe incoming data. TCLK_R/F high
selects the rising edge for clocking data and low selects the
falling edge. If either of the SYNC inputs is high for 5*TCLK
cycles, the data at DIN0-DIN9 is ignored regardless of clock
edge.
After determining which clock edge to use, a start and stop
bit, appended internally, frame the data bits in the register.
The start bit is always high and the stop bit is always low.
The start and stop bits function as the embedded clock bits
in the serial stream.
The Serializer transmits serialized data and clock bits (10+2
bits) from the serial data output (DO
frequency. For example, if TCLK is 66 MHz, the serial rate is
66 x 12 = 792 Mega-bits-per-second. Since only 10 bits are
from input data, the serial “payload” rate is 10 times the
TCLK frequency. For instance, if TCLK = 66 MHz, the pay-
load data rate is 66 x 10 = 660 Mbps. The data source
provides TCLK and must be in the range of 20 MHz to 66
MHz nominal.
The Serializer outputs (DO
nection or in limited multi-point or multi-drop backplanes.
The outputs transmit data when the enable pin (DEN) is
high, PWRDN = high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the Serializer output pins will enter
TRI-STATE.
When the Deserializer synchronizes to the Serializer, the
LOCK pin is low. The Deserializer locks to the embedded
clock and uses it to recover the serialized data. ROUT data
is valid when LOCK is low. Otherwise ROUT0–ROUT9 is
invalid.
The ROUT0-ROUT9 pins use the RCLK pin as the reference
to data. The polarity of the RCLK edge is controlled by the
RCLK_R/F input. See Figure 13.
ROUT(0-9), LOCK and RCLK outputs will drive a maximum
of three CMOS input gates (15 pF load) with a 66 MHz clock.
Resynchronization
When the Deserializer PLL locks to the embedded clock
edge, the Deserializer LOCK pin asserts a low. If the Dese-
rializer loses lock, the LOCK pin output will go high and the
outputs (including RCLK) will enter TRI-STATE.
The user’s system monitors the LOCK pin to detect a loss of
synchronization. Upon detection, the system can arrange to
pulse the Serializer SYNC1 or SYNC2 pin to resynchronize.
Multiple resynchronization approaches are possible. One
recommendation is to provide a feedback loop using the
LOCK pin itself to control the sync request of the Serializer
(SYNC1 or SYNC2). Dual SYNC pins are provided for mul-
tiple control in a multi-drop application. Sending sync pat-
(Continued)
±
) can drive a point-to-point con-
±
) at 12 times the TCLK
3
terns for resynchronization is desirable when lock times
within a specific time are critical. However, the Deserializer
can lock to random data, which is discussed in the next
section.
Random Lock Initialization and
Resynchronization
The initialization and resynchronization methods described
in their respective sections are the fastest ways to establish
the link between the Serializer and Deserializer. However,
the SCAN921224 can attain lock to a data stream without
requiring the Serializer to send special SYNC patterns. This
allows the SCAN921224 to operate in “open-loop” applica-
tions. Equally important is the Deserializer’s ability to support
hot insertion into a running backplane. In the open loop or
hot insertion case, we assume the data stream is essentially
random. Therefore, because lock time varies due to data
stream characteristics, we cannot possibly predict exact lock
time. However, please see Table 1 for some general random
lock times under specific conditions. The primary constraint
on the “random” lock time is the initial phase relation be-
tween the incoming data and the REFCLK when the Dese-
rializer powers up. As described in the next paragraph, the
data contained in the data stream can also affect lock time.
If a specific pattern is repetitive, the Deserializer could enter
“false lock” - falsely recognizing the data pattern as the
clocking bits. We refer to such a pattern as a repetitive
multi-transition, RMT. This occurs when more than one Low-
High transition takes place in a clock cycle over multiple
cycles. This occurs when any bit, except DIN 9, is held at a
low state and the adjacent bit is held high, creating a 0-1
transition. In the worst case, the Deserializer could become
locked to the data pattern rather than the clock. Circuitry
within the SCAN921224 can detect that the possibility of
“false lock” exists. The circuitry accomplishes this by detect-
ing more than one potential position for clocking bits. Upon
detection, the circuitry will prevent the LOCK output from
becoming active until the potential “false lock” pattern
changes. The false lock detect circuitry expects the data will
eventually change, causing the Deserializer to lose lock to
the data pattern and then continue searching for clock bits in
the serial data stream. Graphical representations of RMT are
shown in Figure 1. Please note that RMT only applies to bits
DIN0-DIN8.
Powerdown
When no data transfer occurs, you can use the Powerdown
state. The Serializer and Deserializer use the Powerdown
state, a low power sleep mode, to reduce power consump-
tion. The Deserializer enters Powerdown when you drive
PWRDN and REN low. The Serializer enters Powerdown
when you drive PWRDN low. In Powerdown, the PLL stops
and the outputs enterTRI-STATE, which disables load cur-
rent and reduces supply current to the milliampere range. To
exit Powerdown, you must drive the PWRDN pin high.
Before valid data exchanges between the Serializer and
Deserializer, you must reinitialize and resynchronize the de-
vices to each other. Initialization of the Serializer takes 510
TCLK cycles. The Deserializer will initialize and assert LOCK
high until lock to the Bus LVDS clock occurs.
TRI-STATE
The Serializer enters TRI-STATE when the DEN pin is driven
low. This puts both driver output pins (DO+ and DO−) into
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