SCAN921023SLCX National Semiconductor, SCAN921023SLCX Datasheet - Page 2

• Manufacturer Part Number: SCAN921023SLCX
• Description: IC SERIALIZER 10BIT 49-FBGA
• Manufacturer: National Semiconductor
• Series: SCANr

Specifications of SCAN921023SLCX

• Function: Serializer
• Data Rate: 660Mbps
• Input Type: LVDS
• Output Type: LVDS
• Number Of Inputs: 10
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 49-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Block Diagrams
Functional Description
The SCAN921023 and SCAN921224 are a 10-bit Serializer
and Deserializer chipset designed to transmit data over dif-
ferential backplanes at clock speeds from 20 to 66 MHz. The
chipset is also capable of driving data over Unshielded
Twisted Pair (UTP) cable.
The chipset has three active states of operation: Initializa-
tion, Data Transfer, and Resynchronization; and two passive
states: Powerdown and TRI-STATE. In addition to the active
and passive states, there are also test modes for JTAG
access and at-speed BIST.
The following sections describe each operation and passive
state and the test modes.
Initialization
Initialization of both devices must occur before data trans-
mission begins. Initialization refers to synchronization of the
Serializer and Deserializer PLL’s to local clocks, which may
be the same or separate. Afterwards, synchronization of the
Deserializer to Serializer occurs.
Step 1: When you apply V
rializer, the respective outputs enter TRI-STATE, and on-chip
CC
to both Serializer and/or Dese-
(Continued)
Application
2
power-on circuitry disables internal circuitry. When V
reaches V
ing to a local clock. For the Serializer, the local clock is the
transmit clock (TCLK) provided by the source ASIC or other
device. For the Deserializer, you must apply a local clock to
the REFCLK pin.
The Serializer outputs remain in TRI-STATE while the PLL
locks to the TCLK. After locking to TCLK, the Serializer is
now ready to send data or SYNC patterns, depending on the
levels of the SYNC1 and SYNC2 inputs or a data stream.
The SYNC pattern sent by the Serializer consists of six ones
and six zeros switching at the input clock rate.
Note that the Deserializer LOCK output will remain high
while its PLL locks to the incoming data or to SYNC patterns
on the input.
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete initialization. The Deserializer will lock to
non-repetitive data patterns. However, the transmission of
SYNC patterns enables the Deserializer to lock to the Seri-
alizer signal within a specified time. See Figure 9.
The user’s application determines control of the SYNC1 and
SYNC 2 pins. One recommendation is a direct feedback loop
CC
OK (2.5V) the PLL in each device begins lock-
20000101
20000102
CC