SCAN921023SLCX National Semiconductor, SCAN921023SLCX Datasheet - Page 20

• Manufacturer Part Number: SCAN921023SLCX
• Description: IC SERIALIZER 10BIT 49-FBGA
• Manufacturer: National Semiconductor
• Series: SCANr

Specifications of SCAN921023SLCX

• Function: Serializer
• Data Rate: 660Mbps
• Input Type: LVDS
• Output Type: LVDS
• Number Of Inputs: 10
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 49-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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DIN
TCLKR/F
DO+
DO−
DEN
PWRDN
TCLK
SYNC
DVCC
DGND
AVCC
AGND
TDI
TDO
TMS
TCK
TRST
N/C
ROUT
RCLKR/F
RI+
RI−
PWRDN
LOCK
Serializer Pin Description
Deserializer Pin Description
Pin Name
Pin Name
N/A
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
F5, F7, G4, G5
E1, E2, F2, F4
A3, B1, C1,
D1, D2, D3,
B5, B6, C6,
C5, D4, F6,
C4, C7, D6,
A1, C2, F5,
A5, A6, B4,
A2, A7, B2,
A5, B4, B6,
C3, C4, E5
Ball Id.
G6, G7
Ball Id.
E6, G4
B7, G5
A4, B3
E7, F7
G3
D7
D5
D6
C7
G1
G2
D2
C1
D3
E4
F1
E3
F3
B3
E1
Data Input. LVTTL levels inputs. Data on these pins are loaded into
a 10-bit input register.
Transmit Clock Rising/Falling strobe select. LVTTL level input.
Selects TCLK active edge for strobing of DIN data. High selects
rising edge. Low selects falling edge.
+ Serial Data Output. Non-inverting Bus LVDS differential output.
− Serial Data Output. Inverting Bus LVDS differential output.
Serial Data Output Enable. LVTTL level input. A low puts the Bus
LVDS outputs in TRI-STATE.
Powerdown. LVTTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
Transmit Clock. LVTTL level input. Input for 20 MHz–66 MHz
system clock.
Assertion of SYNC (high) for at least 1024 synchronization symbols
to be transmitted on the Bus LVDS serial output. Synchronization
symbols continue to be sent if SYNC continues to be asserted. TTL
level input. The two SYNC pins are ORed.
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
Test Data Input to support IEEE 1149.1
Test Data Output to support IEEE 1149.1
Test Mode Select Input to support IEEE 1149.1
Test Clock Input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1
Leave open circuit, do not connect
Data Output.
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High selects
rising edge. Low selects falling edge.
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wired OR connections.
20
±
9 mA CMOS level outputs.
Description
Description