UJA1061TW/5V0/C/T, NXP Semiconductors, UJA1061TW/5V0/C/T, Datasheet - Page 10

• Manufacturer Part Number: UJA1061TW/5V0/C/T,
• Description: IC CAN/LIN FAIL-SAFE HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW/5V0/C/T,

• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Applications: Automotive Networking
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 2
• Supply Voltage (max): 27 V or 52 V
• Supply Voltage (min): 5.5 V
• Supply Current (max): 10 mA or 25 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288866518

NXP Semiconductors
6. Functional description
LPC2101_02_03_4
Product data sheet
6.1 Architectural overview
6.2 On-chip flash program memory
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The particular flash implementation in the LPC2101/02/03 allows for full speed execution
also in ARM mode. It is recommended to program performance critical and short code
sections in ARM mode. The impact on the overall code size will be minimal but the speed
can be increased by 30 % over Thumb mode.
The LPC2101/02/03 incorporate a 8 kB, 16 kB or 32 kB flash memory system
respectively. This memory may be used for both code and data storage. Programming of
the flash memory may be accomplished in several ways. It may be programmed in system
via the serial port. The application program may also erase and/or program the flash while
the application is running, allowing a great degree of flexibility for data storage field
firmware upgrades, etc. The entire flash memory is available for user code as the
bootloader resides in a separate memory.
The LPC2101/02/03 flash memory provides a minimum of 100,000 erase/write cycles and
20 years of data-retention memory.
•
•
The standard 32-bit ARM set.
A 16-bit Thumb set.
Rev. 04 — 2 June 2009
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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