UJA1061TW/3V0,518 NXP Semiconductors, UJA1061TW/3V0,518 Datasheet
UJA1061TW/3V0,518
Specifications of UJA1061TW/3V0,518
Related parts for UJA1061TW/3V0,518
UJA1061TW/3V0,518 Summary of contents
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... General description The UJA1061 fail-safe System Basis Chip (SBC) replaces basic discrete components that are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications that control various power and sensor peripherals by using fault-tolerant CAN as the main network interface and LIN as a local sub-bus ...
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... NXP Semiconductors 2. Features and benefits 2.1 General Contains a full set of CAN and LIN ECU functions: CAN transceiver and LIN transceiver Voltage regulator for the microcontroller (3 5.0 V) Separate voltage regulator for the CAN transceiver (5 V) Enhanced window watchdog with on-chip oscillator Serial Peripheral Interface (SPI) for the microcontroller ...
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... NXP Semiconductors 2.4 Power management Smart operating modes and power management modes Cyclic wake-up capability in Standby and Sleep modes Local wake-up input with cyclic supply feature Remote wake-up capability via the CAN-bus and LIN-bus External voltage regulators can easily be incorporated in the power supply system ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name [1] UJA1061TW HTSSOP32 [1] UJA1061TW/5V0 is for the 5 V version; UJA1061TW/3V3 is for the 3.3 V version. 4. Block diagram 32 BAT42 27 BAT14 29 SYSINH INH/LIMP 7 INTN 18 WAKE WAKE 16 TEST CHIP TEMPERATURE 11 SCK 9 SDI SPI 10 SDO 12 SCS 26 RTLIN ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol n.c. n.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCS TXDC RXDC n.c. TEST UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip n. TXDL 4 V1 RXDL ...
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... NXP Semiconductors Table 2. Symbol INH/LIMP WAKE RTL V2 CANH CANL GND RTH LIN RTLIN BAT14 n.c. SYSINH V3 reserved BAT42 The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the printed-circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND for the best EMC performance ...
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... NXP Semiconductors 6. Functional description 6.1 Introduction The UJA1061 combines all peripheral functions around a microcontroller within typical automotive networking applications into one dedicated chip. The functions are as follows: • Power supply for the microcontroller • Power supply for the CAN transceiver • ...
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... NXP Semiconductors mode change via SPI watchdog trigger Normal mode V1: ON SYSINH: HIGH CAN: all modes available flash entry enabled (111/001/111 mode sequence) LIN: all modes available OR mode change to Sleep with pending wake-up watchdog: window INH/LIMP: HIGH/LOW/float EN: HIGH/LOW init Normal mode ...
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... NXP Semiconductors 6.2.1 Start-up mode Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a system reset. The reset source information is provided by the SBC to support different software initialization cycles that depend on the reset event ...
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... NXP Semiconductors Entering Normal mode does not activate the CAN or LIN transceiver automatically. The CAN Mode Control (CMC) bit must be used to activate the CAN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus. The LIN Mode Control (LMC) bit must be used to activate the LIN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the LIN-bus ...
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... NXP Semiconductors When an interrupt event occurs the application software has to read the Interrupt register within t RSTN(INT) entered. If the application has read out the Interrupt register within the specified time, it can decide whether to switch into Normal mode via an SPI access or to stay in Standby mode ...
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... NXP Semiconductors 6.2.7 Flash mode Flash mode can only be entered from Normal mode by entering a specific Flash mode entry sequence. This fail-safe control sequence comprises three consecutive write accesses to the Mode register, within the legal windows of the watchdog, using the operating mode codes 111, 001 and 111 respectively result of this sequence, the SBC will enter Start-up mode and perform a system reset with the related reset source information (bits RSS = 0110) ...
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... NXP Semiconductors The following corrupted watchdog accesses result in an immediate system reset: • Illegal watchdog period coding; only ten different codes are valid • Illegal operating mode coding; only six different codes are valid Any microcontroller driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register ...
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... NXP Semiconductors The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler. The period can be changed within any valid trigger window. Whenever the watchdog is triggered within the window time, the timer will be reset to start a new period. The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period ...
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... NXP Semiconductors If the microcontroller supply current increases above I the watchdog is restarted with the last used watchdog period time and a watchdog restart interrupt is forced, if enabled. In case of a direct mode change towards Standby mode with watchdog OFF selected, the longest possible watchdog period is used. It should be noted that in Sleep mode V1 current monitoring is not active ...
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... NXP Semiconductors The behavior of pin RSTN is illustrated in setting of the RLC bit (defines the reset length). Once an external reset event is detected the system controller enters the Start-up mode. The watchdog now starts to monitor pin RSTN as illustrated in mode is entered as shown RSTN Fig 6. Fig 7. ...
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... NXP Semiconductors Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin RSTN HIGH but pin RSTN level remains LOW for longer than t immediately enters Fail-safe mode since this indicates an application failure. The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin ...
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... NXP Semiconductors The V1 regulator is overload protected. The maximum output current available from pin V1 depends on the voltage applied at pin BAT14 (see total power dissipation should be taken into account. 6.6.2.2 Voltage regulator V2 Voltage regulator V2 provides supply for the CAN transmitter. The pin V2 is intended for the connection of external buffering capacitors ...
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... NXP Semiconductors 6.7 CAN transceiver The integrated fault-tolerant CAN transceiver of the UJA1061 is an advanced ISO11898-3 compliant transceiver and is interoperable with the TJA1054 and TJA1054A stand-alone transceivers. In addition to standard fault-tolerant CAN transceivers the UJA1061 transceiver provides the following features: • Enhanced error handling and reporting of bus and RXD/TXD failures; these failures are separately identified in the System Diagnosis register • ...
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... NXP Semiconductors SBS enters Normal or Flash mode AND CMC = 1 CMC = 0 AND CPNC = 0 On-line mode V2 : ON/OFF (V2D) transmitter: OFF RXDC: wake-up (active LOW) CANL bias V2/floating/(V2D) CPNC = 0 no activity for t > t CAN wake-up filter passed AND CPNC = 0 power-on Fig 8. States of the CAN transceiver In the System Diagnosis register two dedicated CAN status bits (CANMD) are available to signal the mode of the transceiver ...
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... NXP Semiconductors When leaving Active mode the CAN transmitter is disabled and the CAN receiver is monitoring the CAN-bus for a valid wake-up. The CAN termination is then working autonomously. 6.7.1.2 On-line mode In On-line mode the CAN bus pins and RTL and RTH pins are biased to the normal levels. ...
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... NXP Semiconductors between (reverse supply protection) while pin CANL becomes terminated to pin BAT42 (via pin RTH and pin RTL). If pin V2 is disabled due to an overload condition RTH and RTL become floating. 6.7.4 Bus, RXD and TXD failure detection The UJA1061 can distinguish between bus, RXD and TXD failures as indicated in All failures are signalled separately in the CANFD bits in the System Diagnosis register ...
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... NXP Semiconductors 6.7.4.3 GND shift detection The SBC can detect ground shifts in reference to the CAN bus. Two different ground shift detection levels can be selected with the GSTHC bit in the System Configuration register. The failure can be read out in the System Diagnosis register. Any detected or recovered GND shift event is signalled with an interrupt, if enabled ...
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... NXP Semiconductors The LTC bit can be used to set the LIN transceiver to a Listen-only mode. The transmitter output stage is disabled in this mode. When leaving Active mode the LIN transmitter is disabled and the LIN receiver is monitoring the LIN-bus for a valid wake-up. 6.8.1.2 Off-line mode Off-line mode is the low power mode of the LIN transceiver ...
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... NXP Semiconductors RTLIN = ON supplied directly out of BAT42 mode change to Active mode Fig 11. States of the RTLIN pin 6.8.4 LIN slope control The LSC bit in the Physical Layer Control register offers a choice between two LIN slope times, allowing communication kbit/s (normal 10.4 kbit/s (low slope). ...
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... NXP Semiconductors 6.8.6.3 LIN recessive clamping If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter is disabled. The transmitter is reactivated automatically when the LIN bus becomes dominant or manually by setting and clearing the LTC bit. 6.9 Inhibit and limp-home output The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for an extra (external) voltage regulator ‘ ...
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... NXP Semiconductors continuously ON, the WAKE input will be sampled continuously, regardless of the level of bit WSC. The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the System Status register reflect the actual status of pin WAKE. The WAKE port can be disabled by clearing the WEN bit in the System Configuration register. ...
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... NXP Semiconductors 6.13 SPI interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content ...
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... NXP Semiconductors Each register carries 12 data bits; the other 4 bits are used for register selection and read/write definition. 6.13.2 Register overview The SPI interface gives access to all SBC registers; see A0) of the message header define the register address, the third bit is the read register select bit (RRS) to select one out of two possible feedback registers ...
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... NXP Semiconductors Table 5. Mode register bit description (bits and Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only NWP[5:0] see Table OM[2:0] Operating Mode 2 SDM Software Development Mode 1 EN Enable 0 - reserved [1] Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’, while observing the watchdog trigger rules ...
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... NXP Semiconductors Table 6. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 01 (as set in the Special Mode register) Nominal Watchdog Period WDPRE = 10 (as set in the Special Mode register) Nominal Watchdog Period WDPRE = 11 (as set in the Special Mode register) [1] The nominal watchdog periods are directly related to the SBC internal oscillator ...
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... NXP Semiconductors 6.13.4 System Status register This register allows status information to be read back from the SBC. This register can be read in all modes. Table 7. System Status register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO ...
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... NXP Semiconductors Table 7. System Status register bit description Bit Symbol Description 1 ENS Enable status 0 PWONS Power-on reset Status [1] The RSS bits are updated with each reset event and not cleared. The last reset event is captured. 6.13.5 System Diagnosis register This register allows diagnosis information to be read back from the SBC. This register can be read in all modes ...
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... NXP Semiconductors Table 8. System Diagnosis register bit description Bit Symbol Description 3 V2D V2 diagnosis 2 V1D V1 diagnosis 1 and 0 CANMD CAN Mode Diagnosis [1:0] [1] V2D will be set when V2 is reactivated after a failure. See 6.13.6 Interrupt Enable register and Interrupt Enable Feedback register These registers allow setting, clearing and reading back the interrupt enable bits of the SBC ...
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... NXP Semiconductors Table 9. Interrupt Enable register and Interrupt Enable Feedback register bit description Bit Symbol Description 5 CANFIE CAN Failure Interrupt Enable 4 LINFIE LIN Failure Interrupt Enable 3 WIE WAKE Interrupt Enable 2 WDRIE Watchdog Restart Interrupt Enable 1 CANIE CAN Interrupt Enable 0 LINIE LIN Interrupt Enable [1] This bit is cleared automatically upon each overflow event ...
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... NXP Semiconductors Table 10. Interrupt register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only 11 WTI Watchdog Time-out Interrupt 10 OTI OverTemperature Interrupt 9 GSI Ground Shift Interrupt 8 SPIFI SPI clock count Failure Interrupt 7 - reserved 6 VFI Voltage Failure Interrupt 1 ...
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... NXP Semiconductors 6.13.8 System Configuration register and System Configuration Feedback register These registers allow configuration of the behavior of the SBC, and allow the settings to be read back. Table 11. System Configuration register and System Configuration Feedback register bit description Bit Symbol Description 15 and 14 ...
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... NXP Semiconductors 6.13.9 Physical Layer Control register and Physical Layer Control Feedback register These registers allow configuration of the CAN transceiver and LIN transceiver of the SBC and allow the settings to be read back. Table 12. Physical Layer Control register and Physical Layer Control Feedback register bit description ...
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... NXP Semiconductors [3] In case of an RXDC / TXDC interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing the LTC bit under software control. ...
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... NXP Semiconductors 6.13.11 General Purpose registers and General Purpose Feedback registers The UJA1061 offers two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) with no predefined bit definition. These registers can be used by the microcontroller for advanced system diagnosis, or for storing critical system status information outside the microcontroller. After Power-up General Purpose register 0 will contain a ‘ ...
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... NXP Semiconductors 6.13.12 Register configurations at reset At power-on, Start-up and Restart the setting of the SBC registers is predefined. Table 16. System Status register: status at reset Symbol Name RSS Reset Source Status CWS CAN Wake-up Status LWS LIN Wake-up Status EWS Edge Wake-up Status WLS ...
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... NXP Semiconductors Table 20. System Configuration register and System Configuration Feedback register: status at reset Symbol Name GSTHC GND Shift level Threshold Control RLC Reset Length Control V3C V3 Control V1CMC V1 Current Monitor Control WEN Wake Enable WSC Wake Sample Control ILEN INH/LIMP Enable ...
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... NXP Semiconductors Table 22. Special Mode register: status at reset Symbol Name ISDM Initialize Software Development Mode ERREM Error pin emulation mode WDPRE Watchdog Prescale Factor V1RTHC V1 Reset Threshold Control Table 23. General Purpose register 0 and General Purpose Feedback register 0: status at reset Symbol Name ...
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... NXP Semiconductors There are two possibilities to enter Software Development mode. One is by setting the ISDM bit via the Special Mode register; possible only once after a first battery connection while the SBC is in Start-up mode. The second possibility to enter Software Development mode is by applying the correct V applied to pin BAT42 ...
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... ESD performance according to IEC 61000-4 150 pF 330 Ω) of pins CANH, CANL, RTH, RTL, LIN, RTLIN, WAKE, BAT42 [4] and V3 with respect to GND was verified by an external test house. Following results were obtained: a) equal or better than ±6 kV (unaided). b) equal or better than ±20 kV (using external ESD protection: NXP Semiconductors PESD1CAN and PESD1LIN diode). Machine Model (MM 200 pF 0.75 μ Ω. [5] UJA1061_6 ...
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... NXP Semiconductors 8. Thermal characteristics Fig 15. Thermal model of the HTSSOP32 package UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip V1 dissipation V2 dissipation 6 K/W 20 K/W All information provided in this document is subject to legal disclaimers. Rev. 06 — 9 March 2010 UJA1061 V3 dissipation other dissipation 23 K/W ...
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... NXP Semiconductors 9. Static characteristics Table 26. Static characteristics − ° ° +150 5 V;V vj BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Supply; pin BAT42 I BAT42 supply current V1, V2 and V3 off; CAN and BAT42 I additional BAT42 BAT42(add) ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 V;V vj BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I additional BAT14 BAT14(add) supply current [2] Voltage source; pin V1 ; see also V output voltage o(V1) ΔV supply voltage V1 regulation ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 V;V vj BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I undercurrent thH(V1) threshold for watchdog enable I undercurrent thL(V1) threshold for watchdog disable I output current V1 capability Z regulator impedance ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 V;V vj BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter System inhibit output; pin SYSINH BAT42-SYSINH(drop) BAT42 voltage drop |I | leakage current L Inhibit / limp-home output; pin INH/LIMP BAT14-INH(drop) ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 V;V vj BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter V LOW-level input IL(th) threshold voltage Enable output; pin EN I HIGH-level output OH current I LOW-level output OL current V LOW-level output ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 V;V vj BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter V pin CANH wake-up wu(CANH) threshold voltage V pin CANL wake-up wu(CANL) threshold voltage ΔV wake-up threshold wu(CANH-CANL) difference voltage ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 V;V vj BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter LIN transmit data input; pin TXDL V LOW-level input IL voltage V HIGH-level input IH voltage R TXDL pull-up resistor TXDL(pu) LIN receive data output; pin RXDL ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 V;V vj BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter LIN-bus termination resistor connection; pin RTLIN V RTLIN output voltage RTLIN ΔV RTLIN load regulation Active mode; RTLIN I RTLIN pull-up current Active mode ...
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... NXP Semiconductors Fig 16. V1 output voltage (dropout function of battery voltage UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip ( −100 μA −50 mA −120 mA −250 ° ( −100 μA −50 mA −120 mA −250 150 °C. j All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors I BAT14 (mA) (1) Types 5V0 and 3V3. (2) Type 5V0 only BAT14 (mA) (1) Types 5V0 and 3V3. (2) Type 3V3 only Fig 17. V1 quiescent current as a function of output current UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip 10 − ( BAT14 2 (2) 5 ...
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... NXP Semiconductors Fig 18. V1 output voltage as a function of output current PSRR (dB) (1) Type 5V0 only. Fig 19. V1 power supply ripple rejection as a function of frequency UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip 6 type 5V0 V V1 (V) 4 type 3V3 2 0 −40 ...
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... NXP Semiconductors V BAT14 a. Line transient response (mA) b. Load transient response Fig 20. V1 transient response as a function of time UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip 16 (V) V BAT14 100 200 = −5 mA μF; ESR = 0.01 Ω − − 100 200 = μF; ESR = 0.01 Ω; T ...
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... NXP Semiconductors ESR Fig 21. V1 output stability related to ESR value of output capacitor UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip 1 (Ω) −1 10 −2 10 unstable operation area −3 10 −40 0 All information provided in this document is subject to legal disclaimers. Rev. 06 — 9 March 2010 stable operation area − ...
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... NXP Semiconductors a. Switch-on test circuit. b. Behavior Behavior at T Fig 22. Switch-on behavior of V UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip BAT42 BAT14 100 μF/ V BAT 0.1 Ω 100 ( BAT V = 5.5 V BAT BAT ° ( BAT 5.5 V BAT BAT ° ...
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... NXP Semiconductors 10. Dynamic characteristics Table 27. Dynamic characteristics − ° ° 150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see T clock cycle time cyc t enable lead time ...
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... NXP Semiconductors Table 27. Dynamic characteristics − ° ° 150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter t bus failure recovery BUS(fail)(recover) time t TXDC permanent TXDC(dom) dominant disable time t , minimum dominant CANH(d1) t time first pulse for ...
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... NXP Semiconductors Table 27. Dynamic characteristics − ° ° 150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter t t ground shift sampling CANH, CANL time required for CANH, CANL voltage level Δt pulse count PC difference between ...
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... NXP Semiconductors Table 27. Dynamic characteristics − ° ° 150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Battery monitoring t BAT42 LOW time for BAT42(L) setting PWONS Power supply V1; pin clamped LOW V1(CLT) time during ramp- Power supply V2 ...
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... NXP Semiconductors Table 27. Dynamic characteristics − ° ° 150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter t reset lengthening RSTNL time Interrupt output; pin INTN t interrupt release INTN Oscillator f oscillator input osc frequency [1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at T wafer level (pretesting) ...
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... NXP Semiconductors V dif(CANH-CANL) Fig 24. Timing diagram CAN transceiver Fig 25. Timing test circuit for LIN transceiver UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip TXDC V CANL CANH t t(rec-dom RXDC t PHL RXDL 20 pF TXDL All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors t bit V TXDL V BAT42 LIN BUS signal V RXDL1 receiving node 1 t p(rx)f V RXDL2 receiving node 2 Fig 26. Timing diagram LIN transceiver SCS SCK SDI X floating SDO Fig 27. SPI timing UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip t bit t t bus(dom)(max) ...
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... NXP Semiconductors 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip All information provided in this document is subject to legal disclaimers. Rev. 06 — ...
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... NXP Semiconductors 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad side pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 0.95 mm 1.1 0.25 ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. UJA1061_6 Product data sheet Fault-tolerant CAN/LIN fail-safe system basis chip maximum peak temperature = MSL limit, damage level ...
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... NXP Semiconductors 14. Revision history Table 30. Revision history Document ID Release date UJA1061_6 20100309 • Modifications: 3.0 V version (UJA1061TW/3V0) discontinued • Table • Section • Table • Section • Section UJA1061_5 20071122 UJA1061_4 20070427 UJA1061_3 20060627 UJA1061_2 20051122 (9397 750 14201) UJA1061_1 20040322 ...
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... NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any 16. Contact information For more information, please visit: ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 Power management . . . . . . . . . . . . . . . . . . . . . 3 2.5 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 7 6.1 Introduction ...
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... NXP Semiconductors 13 Soldering of SMD packages . . . . . . . . . . . . . . 70 13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 70 13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 70 13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 70 13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 71 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 73 15 Legal information 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 74 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Fault-tolerant CAN/LIN fail-safe system basis chip Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘ ...