UJA1061TW/5V0/C/T, NXP Semiconductors, UJA1061TW/5V0/C/T, Datasheet - Page 12

• Manufacturer Part Number: UJA1061TW/5V0/C/T,
• Description: IC CAN/LIN FAIL-SAFE HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW/5V0/C/T,

• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Applications: Automotive Networking
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 2
• Supply Voltage (max): 27 V or 52 V
• Supply Voltage (min): 5.5 V
• Supply Current (max): 10 mA or 25 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288866518

NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.5.1 Interrupt sources
6.5 Interrupt controller
6.6 Pin connect block
The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored
IRQ, and non-vectored IRQ as defined by programmable settings. The programmable
assignment scheme means that priorities of interrupts from the various peripherals can be
dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine does not need to branch into the interrupt service routine but can
run from the interrupt vector location. If more than one request is assigned to the FIQ
class, the FIQ service routine will read a word from the VIC that identifies which FIQ
source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC
provides the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.
Each peripheral device has one interrupt line connected to the Vectored Interrupt
Controller, but may have several internal interrupt flags. Individual interrupt flags may also
represent more than one interrupt source.
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
The pin control module with its pin select registers defines the functionality of the
microcontroller in a given hardware environment.
After reset all pins of Port 0 are configured as input with the following exceptions: If the
DBGSEL pin is HIGH (Debug mode enabled), the JTAG pins will assume their JTAG
functionality for use with EmbeddedICE and cannot be configured via the pin connect
block.
Rev. 04 — 2 June 2009
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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