WM8776SEFT/V Wolfson Microelectronics, WM8776SEFT/V Datasheet - Page 33

• Manufacturer Part Number: WM8776SEFT/V
• Description: Audio CODECs Stereo CODEC with 5-Ch Mux
• Manufacturer: Wolfson Microelectronics

Specifications of WM8776SEFT/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC Input Mux
ADC Input Mux
Production Data
w
Attenuation
Attenuation
REGISTER
ADDRESS
R14 (0Eh)
R15 (0Fh)
R21 (15h)
R21 (15h)
0001110
0001111
0010101
0010101
ADCR
ADCL
BIT
7:0
7:0
8
8
8
7
6
RAG[7:0]
MUTERA
LAG[7:0]
LRBOTH
MUTELA
LABEL
ZCRA
ZCLA
In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7
(ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated
when the input signal to the gain stage is close to the analogue ground level. This minimises audible
clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will
generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of
12.288MHz). The timeout clock may be disabled by setting TOD.
Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to
write the same attenuation value to both left and right volume control registers, saving on software
writes. The ADC volume and mute also applies to the bypass signal path.
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital high pass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
REGISTER ADDRESS
ADC Control
R11 (0Bh)
0001011
11001111
11001111
DEFAULT
(0dB)
(0dB)
0
0
0
0
0
Attenuation data for Left channel ADC gain in 0.5dB steps. See
Table 15.
Left channel ADC zero cross enable:
Attenuation data for right channel ADC gain in 0.5dB steps. See
Table 15.
Right channel ADC zero cross enable:
Right channel input PGA controlled by left channel register
Mute for left channel ADC
Mute for right channel ADC
BIT
8
ADCHPD
LABEL
0: Zero cross disabled
1: Zero cross enabled
0: Zero cross disabled
1: Zero cross enabled
0 : Right channel uses RAG.
1 : Right channel uses LAG.
0: Mute Off
0: Mute Off
1: Mute on
1: Mute on
DEFAULT
0
DESCRIPTION
ADC High pass filter disable:
0: High pass filter enabled
1: High pass filter disabled
PD, Rev 4.1, September 2008
DESCRIPTION
WM8776
33