MAX98088EWY+T Maxim Integrated Products, MAX98088EWY+T Datasheet - Page 114

• Manufacturer Part Number: MAX98088EWY+T
• Description: Audio CODECs DUAL I2S CODEC AUDIO STEREO
• Manufacturer: Maxim Integrated Products

Specifications of MAX98088EWY+T

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: WLP-63
• Number Of Channels: 2
• Supply Current: 4.5 mA
• Thd Plus Noise: - 77 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Stereo Audio Codec
with FlexSound Technology
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the ICs. The ICs
acknowledge receipt of the address byte during the
master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the IC's internal register address pointer. The pointer
tells the IC where to write the next byte of data. An
acknowledge pulse is sent by the ICs upon receipt of the
address pointer data.
The third byte sent to the ICs contains the data that is
written to the chosen register. An acknowledge pulse
from the ICs signals receipt of the data byte. The
address pointer autoincrements to the next register
address after each received data byte. This autoincre-
ment feature allows a master to write to sequential reg-
isters within one continuous frame. The master signals
the end of transmission by issuing a STOP condition.
Register addresses greater than 0xC7 are reserved. Do
not write to these addresses.
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The IC acknowledges receipt of
its slave address by pulling SDA low during the 9th SCL
clock pulse. A START command followed by a read com-
mand resets the address pointer to register 0x00.
114
Figure 37. Reading One Byte of Data from the ICs
Figure 38. Reading n Bytes of Data from the ICs
S
S
ACKNOWLEDGE FROM MAX98088/
ACKNOWLEDGE FROM MAX98088/
SLAVE ADDRESS
SLAVE ADDRESS
MAX98089
R/W
MAX98089
R/W
O
O
A
ACKNOWLEDGE FROM MAX98088/
A
ACKNOWLEDGE FROM MAX98088/
REGISTER ADDRESS
Read Data Format
REGISTER ADDRESS
REPEATED START
MAX98089
REPEATED START
MAX98089
A
A
Sr
Sr
ACKNOWLEDGE FROM MAX98088/
ACKNOWLEDGE FROM MAX98088/
The first byte transmitted from the ICs is the content of
register 0x00. Transmitted data is valid on the rising
edge of SCL. The address pointer autoincrements after
each read data byte. This autoincrement feature allows
all registers to be read sequentially within one continu-
ous frame. A STOP condition can be issued after any
number of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte to
be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the IC's slave
address with the R/W bit set to 0 followed by the register
address. A REPEATED START condition is then sent fol-
lowed by the slave address with the R/W bit set to 1. The
IC then transmits the contents of the specified register.
The address pointer autoincrements after transmitting
the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowl-
edge from the master and then a STOP condition. Figure
37 illustrates the frame format for reading one byte from
the IC. Figure 38 illustrates the frame format for reading
multiple bytes from the ICs.
SLAVE ADDRESS
SLAVE ADDRESS
MAX98089
R/W
MAX98089
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
1
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
1
A
A
NOT ACKNOWLEDGE FROM MASTER
DATA BYTE
1 BYTE
DATA BYTE
1 BYTE
A
P
A