MAX98088EWY+T Maxim Integrated Products, MAX98088EWY+T Datasheet - Page 83

• Manufacturer Part Number: MAX98088EWY+T
• Description: Audio CODECs DUAL I2S CODEC AUDIO STEREO
• Manufacturer: Maxim Integrated Products

Specifications of MAX98088EWY+T

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: WLP-63
• Number Of Channels: 2
• Supply Current: 4.5 mA
• Thd Plus Noise: - 77 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11. Clock Control Registers (continued)
REGISTER
0x4F
0x50
BIT
7
6
5
4
3
2
1
0
3
2
1
0
DAI2_DAC_LP
DAI1_DAC_LP
DAC2DITHEN
DAC1DITHEN
CGM2_EN
CGM1_EN
NAME
DAI_ DAC Low Power Select.
These bits setup the clocks to be generated from fixed counters that bypass the PLL
for DAC low power mode.
DIA2 DAC Input Dither Enable
DAC2DITHEN is recommended to be set when DAI2_DAC_LP = 0000.
0 = Disabled
1 = Enabled
DIA1 DAC Input Dither 1 Enable
DAC1DITHEN is recommended to be set when DAI1_DAC_LP = 0000.
0 = Disabled
1 = Enabled
DIA2 Clock Gen Module Enable
CGM1_EN has to be set along with CGM2_EN to enable the clock generation for the
DAI2 DAC playback path.
0 = Disabled
1 = Enabled
DIA1/Master Clock Gen Module Enable
CGM1_EN enables the master clock generation, and need to be set for DAC playback
or ADC record.
0 = Disabled
1 = Enabled
VALUE
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
with FlexSound Technology
PLL derived clock
PCLK = 1152 x
PCLK = 1536 x
PCLK = 128 x
PCLK = 192 x
PCLK = 256 x
PCLK = 384 x
PCLK = 768 x
SETTING
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
Stereo Audio Codec
DESCRIPTION
VALUE
0xA
0xB
0xC
0xD
0xE
0x8
0x9
0xF
PCLK = 2304 x
SETTING
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LRCLK
83