MAX98088EWY+T Maxim Integrated Products, MAX98088EWY+T Datasheet - Page 82

• Manufacturer Part Number: MAX98088EWY+T
• Description: Audio CODECs DUAL I2S CODEC AUDIO STEREO
• Manufacturer: Maxim Integrated Products

Specifications of MAX98088EWY+T

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: WLP-63
• Number Of Channels: 2
• Supply Current: 4.5 mA
• Thd Plus Noise: - 77 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Stereo Audio Codec
with FlexSound Technology
82
Table 11. Clock Control Registers (continued)
REGISTER
0x12/0x1A
0x13/0x1B
0x11
BIT
3
2
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
NI1[0]/NI2[0]
PLL1/PLL2
FREQ1
NAME
NI1/
NI2
Exact Integer Mode
Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio.
PLL Mode Enable (Slave Mode Only)
PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK
frequency and automatically sets the LRCLK divider (NI1/NI2).
0 = Disabled
1 = Enabled
Normal Mode LRCLK Divider
When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12
for common NI values.
f
f
Rapid Lock Mode
Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1
to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically
adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is
much closer to the correct value, thus speeding up lock time. Wait one LRCLK period
after programming NI1/NI2 before setting PLL1/PLL2 = 1.
LRCLK
PCLK
48kHz < LRCLK P 96kHz
8kHz P LRCLK P 48kHz
SAMPLE RATE
VALUE
= Prescaled MCLK frequency (PCLK)
= LRCLK frequency
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
SAMPLE RATE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Disabled
DESCRIPTION
DHF1/DHF2
0
1
VALUE
0xA
0xB
0xC
0xD
0x8
0x9
0xE
0xF
NI
NI
=
=
NI1/NI2 FORMULA
65536 96 f
65536 48 f
PCLK = 19.2MHz,
PCLK = 19.2MHz,
PCLK = 12MHz,
PCLK = 12MHz,
LRCLK = 16kHz
PCLK = 13MHz,
PCLK = 13MHz,
LRCLK = 16kHz
PCLK = 16MHz,
PCLK = 16MHz,
LRCLK = 16kHz
LRCLK = 16kHz
SAMPLE RATE
LRCLK = 8kHz
LRCLK = 8kHz
LRCLK = 8kHz
LRCLK = 8kHz
×
×
f
f
PCLK
PCLK
×
×
LRCLK
LRCLK