LAN8700C-AEZG-TR SMSC, LAN8700C-AEZG-TR Datasheet - Page 52

• Manufacturer Part Number: LAN8700C-AEZG-TR
• Description: Ethernet ICs Hi Perform Ethernet PHY
• Manufacturer: SMSC
• Type: Single Chipr

Specifications of LAN8700C-AEZG-TR

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3ab
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 2.2 (12-04-09)
5.4.8
5.4.8.1
5.4.8.2
Ethernet
10/100
MAC
The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address
latched in on reset. The LAN8700/LAN8700i senses each Phy address bit and changes the polarity of
the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active-
low. If the address bit is set as level “0”, the LED polarity will be set to an active-high.
The ACTIVITY LED output is driven active when CRS is active (high). When CRS becomes inactive,
the Activity LED output is extended by 128ms.
The LINK LED output is driven active whenever the PHY detects a valid link. The use of the 10Mbps
or 100Mbps link test status is determined by the condition of the internally determined speed selection.
The SPEED100 LED output is driven active when the operating speed is 100Mbit/s or during Auto-
negotiation. This LED will go inactive when the operating speed is 10Mbit/s or during line isolation
(register 31 bit 5).
The Full-Duplex LED output is driven active low when the link is operating in Full-Duplex mode.
Loopback Operation
The LAN8700/LAN8700i may be configured for near-end loopback and far loopback.
Near-end Loopback
Near-end loopback is a mode that sends the digital transmit data back out the receive data signals for
testing purposes as indicated by the blue arrows in
by setting bit register 0 bit 14 to logic one.
A large percentage of the digital circuitry is operational near-end loopback mode, because data is
routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The COL
signal will be inactive in this mode, unless collision test (bit 0.7) is active. The transmitters are powered
down, regardless of the state of TXEN.
Far Loopback
Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in
Figure
5.3. The far loopback mode is enabled by setting bit register 17 bit 9 to logic one. In this mode,
TXD
RXD
Figure 5.2 Near-end Loopback Block Diagram
Digital
Ethernet Transceiver
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
SMSC
DATASHEET
Analog
52
X
X
Figure
TX
RX
5.2.The near-end loopback mode is enabled
XFMR
SMSC LAN8700/LAN8700i
CAT-5
®
Technology in a Small Footprint
Datasheet