DAC1405D750HW/C1,551 NXP Semiconductors, DAC1405D750HW/C1,551 Datasheet - Page 22

• Manufacturer Part Number: DAC1405D750HW/C1,551
• Description: DAC (D/A Converters) Dual 14BtDAC 750Msps 4xand 8xnterpolating
• Manufacturer: NXP Semiconductors

Specifications of DAC1405D750HW/C1,551

• Number Of Dac Outputs: 4
• Conversion Rate: 650 MSPS
• Resolution: 14 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 0.53 W
• Minimum Operating Temperature: - 40 C
• Supply Current: 5 mA
• Number Of Converters: 2
• Settling Time: 20 ns
• Package / Case: HTQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935290796551

NXP Semiconductors
DAC1405D650
Product data sheet
10.3.1 Dual-port mode
10.3.2 Interleaved mode
10.3 Input data
Table 28.
Table 29.
Default settings are shown highlighted.
The setting applied to MODE_SEL (register 00h[3]; see
defines whether the DAC1405D650 operates in the Dual-port mode or in the Interleaved
mode (see
Table 30.
The data input for Dual-port mode operation is shown in
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
The data input for the Interleaved mode operation is illustrated by
mode
Bit
7 to 0
Bit
7
1 to 0
Bit 3 setting
0
1
Fig 5.
operation”.
Symbol
AUX_B[9:2]
Symbol
AUX_B_PD
AUX_B[1:0]
Dual-port mode
DAC_B_Aux_MSB register (address 1Ch) bit description
DAC_B_Aux_LSB register (address 1Dh) bit description
Mode selection
Table
All information provided in this document is subject to legal disclaimers.
Qn
30).
In
Function
Dual port mode
Interleaved mode
Rev. 3 — 10 September 2010
Dual 14-bit DAC, up to 650 Msps; 2×, 4× and 8× interpolating
LATCH
LATCH
Q
I
Access Value
R/W
R/W
Access Value
R/W
I13 to I0
active
active
2 ×
2 ×
FIR 1
FIR 1
-
0
1
2 ×
2 ×
most significant 8-bits for the auxiliary
Description
DAC B
FIR 2
FIR 2
Description
auxiliary DAC B power
lower 2-bits for the auxiliary DAC B
on
off
Q13 to Q0
active
off
Table 10 on page
Figure 5 “Dual-port
DAC1405D650
2 ×
2 ×
FIR 3
FIR 3
001aaj585
Figure 6 “Interleaved
© NXP B.V. 2010. All rights reserved.
Pin 41
Q13
SELIQ
17) and it
mode”. Each
22 of 45