TSL2581CS TAOS, TSL2581CS Datasheet - Page 9

• Manufacturer Part Number: TSL2581CS
• Description: Light to Digital Converters Light to Digital 30x Sensitivity
• Manufacturer: TAOS

Specifications of TSL2581CS

• Data Bus Width: 16 bit
• Peak Wavelength: 625 nm, 850 nm
• Maximum Operating Frequency: 795 KHz
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Current: 175 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 30 C
• Interface Type: I2C
• Maximum Fall Time: 300 ns
• Maximum Rise Time: 300 ns
• Mounting Style: SMD/SMT
• Resolution: 16 bit
• Package / Case: DFN-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The LUMENOLOGY r Company
When an SMBus Block Write or Block Read is initiated (see description of COMMAND Register), the byte
following the COMMAND byte is ignored but is a requirement of the SMBus specification. This field contains
the byte count (i.e. the number of bytes to be transferred). The TSL2580 (SMBus) device ignores this field and
extracts this information by counting the actual number of bytes transferred before the Stop condition is
detected.
When an I
SMBus protocol specification. Data bytes continue to be transferred from the TSL2581 (I
until a NACK is sent by the Master.
The data formats supported by the TSL2580 and TSL2581 devices are:
D
D
D
For a complete description of SMBus protocols, please review the SMBus Specification at
http://www.smbus.org/specs. For a complete description of I
at http://www.semiconductors.philips.com.
Master transmitter transmits to slave receiver (SMBus and I
−
Master reads slave immediately after the first byte (SMBus only):
−
Combined format (SMBus and I
−
The transfer direction in this case is not changed.
At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter
becomes a master receiver and the slave receiver becomes a slave transmitter.
During a change of direction within a transfer, the master repeats both a START condition and the slave
address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and a STOP condition.
2
C Write or I
A
P
Rd
S
Sr
Wr
X
...
Figure 6. SMBus and I
2
C Read (Combined Format) is initiated, the byte count is also ignored but follows the
Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)
Stop Condition
Read (bit value of 1)
Start Condition
Repeated Start Condition
Write (bit value of 0)
Shown under a field indicates that that field is required to have a value of X
Continuation of protocol
Master-to-Slave
Slave-to-Master
1
S
Slave Address
r
7
2
C):
www.taosinc.com
Wr
2
1
C Packet Protocol Element Key
A
X
1
Data Byte
2
C protocols, please review the I
8
2
C):
LIGHT-TO-DIGITAL CONVERTER
r
1
A
X
1
P
TSL2580, TSL2581
Copyright E 2010, TAOS Inc.
2
C) device to Master
TAOS098 − MARCH 2010
2
C Specification
9