PIC18F6585-I/L Microchip Technology, PIC18F6585-I/L Datasheet - Page 31

• Manufacturer Part Number: PIC18F6585-I/L
• Description: Microcontrollers (MCU) 48KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6585-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 48 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If the main oscillator is configured for HS mode with
PLL active, an oscillator start-up time (T
additional PLL time-out (T
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for HS-PLL mode, is shown in Figure 2-10.
FIGURE 2-10:
FIGURE 2-11:
 2004 Microchip Technology Inc.
Program Counter
Program Counter
Note:
Internal System
Internal System
(OSCCON<0>)
(OSCCON<0>)
PLL Clock
PLL Clock
T1OSI
T1OSI
OSC1
OSC1
Clock
Clock
Input
T
Input
SCS
SCS
OST
= 1024 T
Q4
PC
Q4
PC
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(HS WITH PLL ACTIVE, SCS1 = 1)
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(EC WITH PLL ACTIVE, SCS1 = 1)
OSC
PLL
(drawing not to scale).
Q1
Q1
) will occur. The PLL time-
T
OST
T
PLL
OST
T
PLL
PIC18F6585/8585/6680/8680
) plus an
T
PC + 2
T
PC + 2
OSC
OSC
1
1
If the main oscillator is configured for EC mode with PLL
active, only the PLL time-out (T
time-out is typically 2 ms and allows the PLL to lock to
the main oscillator frequency. A timing diagram, indicat-
ing the transition from the Timer1 oscillator to the main
oscillator for EC with PLL active, is shown in Figure 2-11.
2
2
3
3
T
T
SCS
SCS
T
4
T
4
T
T
1
1
P
P
5
5
6
6
7
7
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
8
8
PLL
) will occur. The PLL
DS30491C-page 29
Q1 Q2
Q1 Q2
PC + 4
PC + 4
Q3
Q3
Q4
Q4