PIC18F6585-I/L Microchip Technology, PIC18F6585-I/L Datasheet - Page 47
PIC18F6585-I/L
Manufacturer Part Number
PIC18F6585-I/L
Description
Microcontrollers (MCU) 48KB 3328 RAM 52 I/O
Manufacturer
Microchip Technology
Datasheet
1.PCM18XK1.pdf
(496 pages)
Specifications of PIC18F6585-I/L
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SPI/AUSART/CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
48 KB
Package / Case
PLCC-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TABLE 3-3:
2004 Microchip Technology Inc.
B3D4
B3D3
B3D2
B3D1
B3D0
B3DLC
B3EIDL
B3EIDH
B3SIDL
B3SIDH
B3CON
B2D7
B2D6
B2D5
B2D4
B2D3
B2D2
B2D1
B2D0
B2DLC
B2EIDL
B2EIDH
B2SIDL
B2SIDH
B2CON
B1D7
B1D6
B1D5
B1D4
B1D3
B1D2
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1:
Register
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
2:
3:
4:
5:
6:
7:
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 3-2 for Reset value for specific condition.
Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.
This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
PIC18F6585/8585/6680/8680
Brown-out Reset
Power-on Reset,
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
RESET Instruction
MCLR Resets
Stack Resets
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDT Reset
Wake-up via WDT
or Interrupt
DS30491C-page 45
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
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