LC4064ZE-5TN100C Lattice, LC4064ZE-5TN100C Datasheet - Page 11

• Manufacturer Part Number: LC4064ZE-5TN100C
• Description: CPLD - Complex Programmable Logic Devices 64MC 64 I/O Ultra Low Power 1.8V
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4064ZE-5TN100C

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Maximum Operating Frequency: 277.78 MHz
• Delay Time: 5.8 ns
• Number Of Programmable I/os: 64
• Operating Supply Voltage: 1.8 V
• Supply Current: 0.08 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 1.9 V
• Supply Voltage (min): 1.7 V
• Programmable Type: CPLD
• Voltage - Input: 1.7 V ~ 1.9 V
• Speed: 5.8ns
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9. Power Guard
All the I/O pins in a block share a common Power Guard Enable signal. For a block of I/Os, this signal is called a
Block Input Enable (BIE) signal. BIE can be internally generated using MC logic, or could come from external
sources using one of the user I/O or input pins.
Any I/O pin in the block can be programmed to ignore the BIE signal. Thus, the feature can be enabled or disabled
on a pin-by-pin basis.
Figure 10 shows Power Guard and BIE across multiple I/Os in a block that has eight I/Os.
Figure 10. Power Guard and BIE in a Block with 8 I/Os
Block Input Enable (BIE)
From Block PT. The Block PT
is part of the block AND Array,
and can be driven by signals
from the GRP.
D
Power Guard
To Macrocell
To GRP
To Macrocell
To GRP
To Macrocell
To GRP
E
0
1
11
Q
ispMACH 4000ZE Family Data Sheet
Power Guard
Power Guard
Power Guard
0
1
0
1
0
1
I/O 0
I/O 1
I/O 7