LC4064ZE-5TN100C Lattice, LC4064ZE-5TN100C Datasheet - Page 13

• Manufacturer Part Number: LC4064ZE-5TN100C
• Description: CPLD - Complex Programmable Logic Devices 64MC 64 I/O Ultra Low Power 1.8V
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4064ZE-5TN100C

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Maximum Operating Frequency: 277.78 MHz
• Delay Time: 5.8 ns
• Number Of Programmable I/os: 64
• Operating Supply Voltage: 1.8 V
• Supply Current: 0.08 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 1.9 V
• Supply Voltage (min): 1.7 V
• Programmable Type: CPLD
• Voltage - Input: 1.7 V ~ 1.9 V
• Speed: 5.8ns
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The block-level OE PT of each GLB is also tied to Block Input Enable (BIE) of that block. Hence, for a 256-macro-
cell device (with 16 blocks), each block's BIE signal is driven by block-level OE PT from each block.
Figure 11. Global OE Generation for All Devices Except ispMACH 4032ZE
Figure 12. Global OE Generation for ispMACH 4032ZE
On-Chip Oscillator and Timer
An internal oscillator is provided for use in miscellaneous housekeeping functions such as watchdog heartbeats,
digital de-glitch circuits and control state machines. The oscillator is disabled by default to save power. Figure 13
shows the block diagram of the oscillator and timer block.
Shared PTOE
(Block 0)
Shared PTOE
(Block n)
Shared PTOE
(Block 0)
Shared PTOE
(Block 1)
Internal Global OE
Internal Global OE
Fuse connection
Hard wired
(4 lines)
PT Bus
(2 lines)
PT Bus
Fuse connection
Hard wired
BIE0
BIE1
BIE0
BIEn
Global OE
13
Global OE
Global
Fuses
Global
Fuses
ispMACH 4000ZE Family Data Sheet
Global OE Bus
to I/O cells
GOE (3:0)
4-Bit
Global OE Bus
to I/O cells
GOE (0:3)
4-Bit