A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 107

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4 – SmartFusion Programming
In-System Programming
SmartFusion devices have three separate flash areas that can be programmed:
There are essentially three methodologies for programming these areas:
Programming, whether ISP or IAP methodologies are employed, can be done in two ways:
In-System Programming is performed with the aid of external JTAG programming hardware.
describes the JTAG programming hardware that will program a SmartFusion device and
defines the JTAG pins that provide the interface for the programming hardware.
Table 4-1 • Supported JTAG Programming Hardware
Table 4-2 • SmartFusion JTAG Pin Descriptions
Dongle
FlashPro3/4
ULINK Pro
ULINK2
IAR J-Link
Notes:
1. SWD = ARM Serial Wire Debug
2. SWV = ARM Serial Wire Viewer
3. Planned support
Pin Name
JTAGSEL
TRSTB
TCK
TMS
TDI
TDO
1. The FPGA fabric
2. The embedded nonvolatile memories (eNVMs)
3. The embedded flash ROM (eFROM)
1. In-system programming (ISP)
2. In-application programming (IAP)—only the FPGA Fabric and the eNVM
3. Pre-programming (non-ISP)
1. Securely using the on chip AES decryption logic
2. In plain text
Products
Source
ARM Cortex-M3 or FPGA test access port (TAP) controller selection
Test reset bar
Test clock
Test mode select
Test data input
Test data output
Group
SoC
Keil
Keil
IAR
JTAG
Yes
Yes
Yes
Yes
R e v i s i o n 6
SWD
Yes
Yes
Yes
No
1
Description
SWV
Yes
Yes
Yes
No
2
Program
FPGA
Yes
Yes
Yes
Yes
3
3
3
Program
eFROM
Yes
Yes
Yes
Yes
3
3
3
Program
Table 4-1
Table 4-2
eNVM
Yes
Yes
Yes
Yes
4 -5