A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 23

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS / 3.3 V LVCMOS – Schmitt trigger
2.5 V LVCMOS
2.5 V LVCMOS – Schmitt trigger
1.8 V LVCMOS
1.8 V LVCMOS – Schmitt trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
LVPECL
Note:
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
Single-Ended
*Dynamic power consumption is given for standard load and software default drive strength and output slew.
Applicable to MSS I/O Banks
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Applicable to MSS I/O Banks
C
C
LOAD
LOAD
10
10
10
10
35
35
35
35
10
10
–
–
(pF)
(pF)
VCCMSSIOBx (V)
VCCFPGAIOBx
VCCMSSIOBx (V)
R e v i s i o n 6
3.3
(V)
2.5
3.3
2.5
1.8
1.5
3.3
2.5
1.8
1.5
3.3
3.3
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
SmartFusion Intelligent Mixed Signal FPGAs
Static Power
Static Power
PDC8 (mW)
PDC8 (mW)
Static Power
PDC7 (mW)
19.54
7.74
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
*
PAC10 (µW/MHz)
PAC10 (µW/MHz)
Dynamic Power
Dynamic Power
PAC9 (µW/MHz)
Dynamic Power
155.65
475.66
270.50
152.17
104.44
202.69
202.69
164.99
88.26
88.23
45.03
31.01
17.21
20.00
5.55
7.03
2.61
2.72
1.98
1.93
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