LFE2-12E-5FN256C Lattice, LFE2-12E-5FN256C Datasheet - Page 103

• Manufacturer Part Number: LFE2-12E-5FN256C
• Description: FPGA - Field Programmable Gate Array 12K LUTs 193 I/O DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFE2-12E-5FN256C

• Number Of Macrocells: 12000
• Number Of Programmable I/os: 193
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• No. Of Logic Blocks: 12000
• No. Of Macrocells: 6000
• No. Of Speed Grades: 5
• Total Ram Bits: 221Kbit
• No. Of I/o's: 193
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Switching Test Conditions
Figure 3-22 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-19.
Figure 3-22. Output Test Load, LVTTL and LVCMOS Standards
Table 3-19. Test Fixture Required Components, Non-Terminated Interfaces
LVTTL and other LVCMOS settings (L -> H, H -> L)
LVCMOS 2.5 I/O (Z -> H)
LVCMOS 2.5 I/O (Z -> L)
LVCMOS 2.5 I/O (H -> Z)
LVCMOS 2.5 I/O (L -> Z)
Note: Output test conditions for all other interfaces are determined by the respective standards.
Test Condition
*CL Includes Test Fixture and Probe Capacitance
DUT
V
R1
R2
T
1M
100
R



1
3-51
1M
100
R



CL*
2
Test Poi nt
0pF
C
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
L
LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = V
LVCMOS 1.8 = V
LVCMOS 1.5 = V
LVCMOS 1.2 = V
V
V
V
V
OH
OL
CCIO
CCIO
+ 0.10
- 0.10
/2
/2
Timing Ref.
CCIO
CCIO
CCIO
CCIO
/2
/2
/2
/2
V
V
CCIO
CCIO
V
—
—
—
—
—
—
—
T