LFE2-12E-5FN256C Lattice, LFE2-12E-5FN256C Datasheet - Page 17

• Manufacturer Part Number: LFE2-12E-5FN256C
• Description: FPGA - Field Programmable Gate Array 12K LUTs 193 I/O DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFE2-12E-5FN256C

• Number Of Macrocells: 12000
• Number Of Programmable I/os: 193
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• No. Of Logic Blocks: 12000
• No. Of Macrocells: 6000
• No. Of Speed Grades: 5
• Total Ram Bits: 221Kbit
• No. Of I/o's: 193
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12.
Figure 2-12. Edge Clock Sources
From Routing
From Routing
Sources for left edge clocks
Input
Input
DLL
PLL
Clock
Clock
Input
Input
DLLDELA
GPLL
DLL
Routing
Routing
From
From
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Clock Input
Clock Input
2-14
Clock Input
Clock Input
Routing
Routing
From
From
Sources for top
LatticeECP2/M Family Data Sheet
bottom edge
Sources for
edge clocks
clocks
Sources for right edge clocks
GPLL
DLL
DLLDELA
Architecture
From Routing
From Routing
Clock
Clock
Input
Input
Input
Input
DLL
PLL