LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 137
LFXP2-8E-5TN144I
Manufacturer Part Number
LFXP2-8E-5TN144I
Description
FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5TN144I
Number Of Macrocells
8000
Number Of Programmable I/os
100
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Use of the Pre-Map Preference Editor
Clock preferences can be set in the Pre-Map Preference Editor. Figure 9-12 shows an example screen shot. The
Pre-Map Preference Editor is a part of the ispLEVER Design Planner.
Figure 9-12. Pre-Map Preference Editor Example
Clock Dividers (CLKDIV)
The clock divider divides the high-speed clock by 1, 2, 4 or 8. All the outputs have matched input to output delay.
CLKDIV can take as its input the edge clocks and the CLKOP of the PLL. The divided outputs drive the primary
clock and are also available for general routing or secondary clocks. The clock dividers are used for providing the
low speed FPGA clocks for shift registers (x2, x4, x8) and DDR/SPI4 I/O logic interfaces.
CLKDIV Primitive Definition
Users can instantiate CLKDIV in the source code as defined in this section. Figure 9-13 and Tables 9-8 and 9-9
describe the CLKDIVB definitions.
Figure 9-13. CLKDIV Primitive Symbol
CLKI
RST
RELEASE
CLKDIVB
9-15
CDIV1
CDIV2
CDIV4
CDIV8
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
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