LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 141

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
CLKDIV Inputs-to-Outputs Delay Matching
Figure 9-17. CLKDIV Inputs-to-Outputs Delay Matching
DCS (Dynamic Clock Select)
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock
sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled.
There are two DCSs for each quadrant.
The outputs of the DCS then reach primary clock distribution via the feedlines. Figure 9-18 shows the block dia-
gram of the DCS.
Figure 9-18. DCS Primitive Symbol
DCS Primitive Definition
Table 9-10 defines the I/O ports of the DCS block. There are eight modes to select from. Table 9-11 describes how
each mode is configured.
Table 9-10. DCS I/O Definition
CLKI
CDIV1
CDIV2
CDIV4
CDIV8
Input
Output
I/O
DCSOUT
Name
CLK0
CLK1
SEL
CLK0
CLK1
SEL
9-19
DCS
DCSOUT
Input Clock Select
Clock Input 1
Clock input 0
Clock Output
Description
LatticeXP2 sysCLOCK PLL
Design and Usage Guide