LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 231
LFXP2-8E-5TN144I
Manufacturer Part Number
LFXP2-8E-5TN144I
Description
FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5TN144I
Number Of Macrocells
8000
Number Of Programmable I/os
100
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
IDDRX2B
This module is used when a gearing function is required. This primitive inputs the DDR data at both edges of the
edge clock and generates four streams of data aligned to SCLK. SCLK is always half the frequency of ECLK. It is
recommended that the CLKDIV module or PLL be used to generate the SCLK from the ECLK.
Figure 11-32 shows the primitive symbol for the IDDRX2B mode.
Figure 11-32. IDDRX2B Symbol
Table 11-8 lists the port names and descriptions for the IDDRX2B primitive.
Table 11-8. IDDRX2B Port Names
Figure 11-33 shows the LatticeXP2 Input Register Block configured in the IDDRX2B mode. The DDR registers and
the first set of synchronization registers are clocked by the ECLK input. The SCLK is used to clock the third stage
of register. This primitive will output four streams of data. The 2x gearing function is implemented by using the syn-
chronization registers of the complementary PIO. The clock transfer registers are shared with the output register
block.
D
ECLK
SCLK
CE
RST
QA0, QA1
QB0, QB1
Port Name
I/O
O
O
I
I
I
I
I
DDR data
This clock can be connected to the fast edge clock
This clock should be connected to the FPGA clock
Clock enable signal
Reset to the DDR register
Data at the positive edge of the clock
Data at the negative edge of the clock
ECLK
SCLK
CE
RST
D
IDDRX2B
11-27
QA0
QA1
QB0
QB1
Description
LatticeXP2 High-Speed I/O Interface
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