LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 35
LFXP2-8E-5TN144I
Manufacturer Part Number
LFXP2-8E-5TN144I
Description
FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5TN144I
Number Of Macrocells
8000
Number Of Programmable I/os
100
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The
overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element.
Figure 2-21. MAC sysDSP
Multiplicand
Multiplier
Signed A
Signed B
Addn
Accumsload
Serial Register B in
n
Input Data
Register B
n
n
SROB
n
Register
Register
Register
Register
Input
Input
Input
Input
m
Input Data
Register A
m
n
SROA
Serial Register A in
m
Register
Register
Register
Register
Pipeline
Pipeline
Pipeline
Pipeline
m
n
2-21
To Accumulator
To Accumulator
To Accumulator
To Accumulator
Multiplier
Register
Pipeline
x
(default)
m+n
Accumulator
CLK (CLK0,CLK1,CLK2,CLK3)
RST(RST0,RST1,RST2,RST3)
CE (CE0,CE1,CE2,CE3)
LatticeXP2 Family Data Sheet
m+n+16
(default)
Preload
(default)
m+n+16
Architecture
Output
Overflow
signal
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