LFXP2-8E-7FT256C Lattice, LFXP2-8E-7FT256C Datasheet - Page 112

• Manufacturer Part Number: LFXP2-8E-7FT256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-7FT256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 8-8. IO_TYPE Attribute Values
OPENDRAIN
LVCMOS and LVTTL I/O standards can be set to open drain configuration by using the OPENDRAIN attribute.
Values: ON, OFF
Default: OFF
DRIVE
The DRIVE attribute will set the programmable drive strength for the output standards that have programmable
drive capability
DEFAULT
LVDS 2.5V
RSDS
Emulated LVDS 2.5V
Bus LVDS 2.5V
LVPECL 3.3V
HSTL18 Class I and II
Differential HSTL 18 Class I and II
HSTL 15 Class I
Differential HSTL 15 Class I
SSTL 33 Class I and II
Differential SSTL 33 Class I and II
SSTL 25 Class I and II
Differential SSTL 25 Class I and II
SSTL 18 Class I and II
Differential SSTL 18 Class I and II
LVTTL
3.3V LVCMOS
2.5V LVCMOS
1.8V LVCMOS
1.5V LVCMOS
1.2V LVCMOS
3.3V PCI
MLVDS
1. These differential standards are implemented by using a complementary 
LVCMOS driver with external resistor pack.
sysIO Signaling Standard
8-8
LVCMOS25
LVDS25
RSDS
LVDS25E
BLVDS25
LVPECL33
HSTL18_I, HTSL18_II
HSTL18D_I, HSTL18D_II
HSTL15_I
HSTL15D_I
SSTL33_I, SSTL33_II
SSTL33D_I, SSTL3D_II
SSTL25_I,SSTL25_II
SSTL25D_I, SSTL25D_II
SSTL18_I, SSTL18_II
SSTL18D_I,SSTL18D_II
LVTTL33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33
MLVDS
1
1
IO_TYPE
1
1
1
LatticeXP2 sysIO Usage Guide