LFXP2-8E-7FT256C Lattice, LFXP2-8E-7FT256C Datasheet - Page 120

• Manufacturer Part Number: LFXP2-8E-7FT256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-7FT256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 sysIO Usage Guide
Appendix B. sysIO Attributes Using the Design Planner User Interface
Designers can assign sysIO buffer attributes using the Design Planner GUI available in the ispLEVER design tool.
The Pin Attribute Sheet list all the ports in a design and all the available sysIO attributes as preferences. By clicking
on each of these cells, a list of all the valid I/O preference for that port is displayed. Each column takes precedence
over the next. Therefore, when a particular IO_TYPE is chosen, the DRIVE, PULLMODE and SLEWRATE columns
will only list the valid combinations for that IO_TYPE. The pin locations can be locked using the pin location column
of the Pin Attribute sheet. Right-clicking on a cell will list the available pin locations. The Spreadsheet View will also
conduct a DRC check to search for any incorrect pin assignments.
Designers can enter DIN/DOUT preferences using the Cell Attributes sheet of the Preference Editor. All the prefer-
ences assigned using the Preference Editor are written into the preference file (.prf).
Figures 8-2 and 8-3 show the Pin Attribute sheet and the Cell Attribute sheet views of the preference editor. For fur-
ther information on how to use the Preference Editor, refer to the ispLEVER Help documentation in the Help menu
option of the software.
Figure 8-2. Port Attributes Tab
Figure 8-3. Cell Attributes Tab
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