LFXP2-8E-7FT256C Lattice, LFXP2-8E-7FT256C Datasheet - Page 5
![FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -7 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-8E-7FT256C
Manufacturer Part Number
LFXP2-8E-7FT256C
Description
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -7 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-7FT256C
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-7FT256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 5 of 341
- Download datasheet (10Mb)
Lattice Semiconductor
LatticeXP2 sysCLOCK PLL Design and Usage Guide
Differential I/O Implementation......................................................................................................................... 8-11
Technical Support Assistance.......................................................................................................................... 8-11
Revision History ............................................................................................................................................... 8-11
Appendix A. HDL Attributes for Synplicity
Appendix B. sysIO Attributes Using the Design Planner User Interface .......................................................... 8-16
Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-17
Introduction ........................................................................................................................................................ 9-1
Clock/Control Distribution Network .................................................................................................................... 9-1
LatticeXP2 Top Level View ................................................................................................................................ 9-1
Primary Clocks ................................................................................................................................................... 9-2
Secondary Clocks .............................................................................................................................................. 9-2
Edge Clocks ....................................................................................................................................................... 9-2
Primary Clock Note ............................................................................................................................................ 9-3
Specifying Clocks in the Design Tools ............................................................................................................... 9-3
Global Primary Clock and Quadrant Primary Clock ........................................................................................... 9-3
sysCLOCK™ PLL .............................................................................................................................................. 9-4
Functional Description........................................................................................................................................ 9-5
PLL Inputs and Outputs ..................................................................................................................................... 9-5
PLL Attributes..................................................................................................................................................... 9-7
LatticeXP2 PLL Primitive Definition.................................................................................................................... 9-8
LVDS....................................................................................................................................................... 8-11
BLVDS .................................................................................................................................................... 8-11
RSDS ...................................................................................................................................................... 8-11
LVPECL .................................................................................................................................................. 8-11
Differential SSTL and HSTL.................................................................................................................... 8-11
MLVDS.................................................................................................................................................... 8-11
VHDL Synplicity/Precision RTL Synthesis .............................................................................................. 8-12
Verilog Synplicity..................................................................................................................................... 8-14
Verilog Precision ..................................................................................................................................... 8-15
IOBUF ..................................................................................................................................................... 8-17
LOCATE.................................................................................................................................................. 8-17
USE DIN CELL........................................................................................................................................ 8-18
USE DOUT CELL.................................................................................................................................... 8-18
GROUP VREF ........................................................................................................................................ 8-18
Primary-Pure and Primary-DCS................................................................................................................ 9-3
Global Primary Clock ................................................................................................................................ 9-3
Quadrant Primary Clock............................................................................................................................ 9-4
PLL Divider and Delay Blocks................................................................................................................... 9-5
CLKI Input ................................................................................................................................................. 9-5
RST Input .................................................................................................................................................. 9-5
RSTK Input................................................................................................................................................ 9-6
CLKFB Input.............................................................................................................................................. 9-6
CLKOP Output .......................................................................................................................................... 9-6
CLKOS Output with Phase and Duty Cycle Select ................................................................................... 9-6
CLKOK Output with Lower Frequency ...................................................................................................... 9-6
CLKOK2 Output ........................................................................................................................................ 9-6
LOCK Output............................................................................................................................................. 9-6
Dynamic Phase and Dynamic Duty Cycle Adjustment.............................................................................. 9-6
WRDEL (Write Delay) ............................................................................................................................... 9-7
FIN ............................................................................................................................................................ 9-7
CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV ................................................................................ 9-7
FREQUENCY_PIN_CLKI, FREQUENCY_PIN_CLKOP, FREQUENCY_PIN_CLKOK ............................ 9-7
CLKOP Frequency Tolerance ................................................................................................................... 9-7
®
and Precision
4
®
RTL Synthesis...................................................... 8-12
LatticeXP2 Family Handbook
Table of Contents
Related parts for LFXP2-8E-7FT256C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LFXP2-8E-5FTN256I](/photos/16/14/161486/bga256_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5FTN256C](/photos/16/15/161505/landingpagelatticexp2_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5TN144I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5TN144C](/photos/16/15/161505/landingpagelatticexp2_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 8K LUTs 100I/O Inst- on DSP 1.2V -5 Spd
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5QN208C](/photos/19/3/190392/4582503_tmb.jpg)
Part Number:
Description:
IC, LATTICEXP2 FPGA, 435MHZ, QFP-208
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFXP2-8E-7TN144C](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeXP2 Family 8000 Cells Flash Technology 1.2V 144-Pin TQFP
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFXP2-8E-6QN208C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 8KLUTS 146I/O 208PQFP
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-6TN144C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 8KLUTS 100I/O 144TQFP
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-6MN132C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 8KLUTS 86I/O 132CSBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5MN132I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 8KLUTS 86I/O 132CSBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5QN208I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 8KLUTS 146I/O 208PQFP
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-6FTN256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 8KLUTS 201I/O 256FTBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5MG132C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 8KLUTS 86I/O 132-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5M132I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 8KLUTS 86I/O 132-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-8E-5FT256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 8KLUTS 201I/O 256-BGA
Manufacturer:
Lattice
Datasheet: