PCF8564ACX9/B/1,02 NXP Semiconductors, PCF8564ACX9/B/1,02 Datasheet - Page 17

• Manufacturer Part Number: PCF8564ACX9/B/1,02
• Description: IC RTC/CALENDAR
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF8564ACX9/B/1,02

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: Die
• Function: Serial Clock, Alarm, Calendar, Timer, Timer Interrupt
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 1700 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 568-6424-2; PCF8564ACX9/B/1,02

NXP Semiconductors
PCF8564A
Product data sheet
8.8.2 Register Timer
8.9.1 Operation example
8.9 EXT_CLK test mode
Table 24.
Table 25.
The timer register is an 8-bit binary countdown timer. It is enabled or disabled via the timer
control register. The source clock for the timer is also selected by the timer control
register. Other timer properties such as single or periodic interrupt generation are
controlled via the register Control_2 (address 01h).
For accurate read back of the count down value, the I
operating at a frequency of at least twice the selected timer clock. Since it is not possible
to freeze the countdown timer counter during read back, it is recommended to read the
register twice and check for consistent results.
The test mode is entered by setting the TEST1 bit of register Control_1 to logic 1. The
CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz signal
with that applied to the CLKOUT pin. Every 64 positive edges applied to CLKOUT then
generates an increment of one second.
The signal applied to the CLKOUT pin should have a minimum pulse width of 300 ns and
a maximum period of 1000 ns. The 64 Hz clock, now sourced from CLKOUT, is divided
down to 1 Hz by a 2
state by using the STOP bit. When the STOP bit is set, the prescaler is reset to logic 0.
(STOP must be cleared before the prescaler can operate.)
From a STOP condition, the first 1 second increment will take place after 32 positive
edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the prescaler can be made.
Bit
7 to 0 TIMER_VALUE[7:0] 00h to FFh countdown value = n;
Bit
7
128
1. Set EXT_CLK test mode (Bit 7 Control_1 = 1).
2. Set STOP (Bit 5 Control_1 = 1).
3. Clear STOP (Bit 5 Control_1 = 0).
4. Set time registers to desired value.
5. Apply 32 clock pulses to CLKOUT.
Symbol
Timer - timer register (address 0Fh) bit description
Timer register bits value range
6
64
All information provided in this document is subject to legal disclaimers.
6
Rev. 02 — 30 September 2010
divide chain called a prescaler. The prescaler can be set to a known
5
32
Value
4
16
Description
CountdownPeriod
3
8
2
C-bus clock (SDA) must be
=
2
4
-------------------------------------------------------------- -
SourceClockFrequency
Real time clock and calendar
PCF8564A
1
2
n
© NXP B.V. 2010. All rights reserved.
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