pcf8564a NXP Semiconductors, pcf8564a Datasheet
pcf8564a
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pcf8564a Summary of contents
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... PCF8564A Real time clock and calendar Rev. 1 — 8 October 2009 1. General description The PCF8564A is a CMOS consumption. A programmable clock output, interrupt output and voltage low detector are also provided. All addresses and data are transferred serially via a two-line bidirectional 2 I C-bus. Maximum bus speed is 400 kbit/s. The built-in word address register is incremented automatically after each written or read data byte ...
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... PCF8564AU Die type 2 PCF8564AU/5BB/1 PCF8564AU PCF8564AU/5GB/1 PCF8564AU PCF8564AU/10AB/1 PCF8564AU Die type 3 PCF8564ACX9/1 PCF8564ACX9 wafer level chip-size package; PCF8564ACX9/B/1 PCF8564ACX9 wafer level chip-size package; [1] Not to be used for new designs. 5. Marking Table 2. Type number Die type 1 PCF8564AU/5BD/1 PCF8564AU/5GE/1 PCF8564AU/10AA/1 Die type 2 PCF8564AU/5BB/1 ...
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... OSCI OSCILLATOR 32.768 kHz OSCO MONITOR POWER ON RESET VDD VSS WATCH DOG 2 SDA I C INTERFACE SCL PCF8564A Fig 1. Block diagram of PCF8564A PCF8564A_1 Product data sheet DIVIDER CONTROL 00h Control_1 01h Control_2 0Dh CLKOUT_ctrl TIME 02h Seconds 03h Minutes 04h Hours 05h ...
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... Real time clock and calendar 9 OSCI OSCO 0 INT PCF8564ACX 013aaa033 Viewed from bump side. For mechanical details, see Figure 28. Pinning diagram of PCF8564ACX9 but should not be electrically contacted. SS © NXP B.V. 2009. All rights reserved. CLKOE V DD CLKOUT SCL SDA ...
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... NXP Semiconductors 8. Functional description The PCF8564A contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which provides the source clock for the RTC, a programmable clock output, a timer, a voltage low detector, and a 400 kHz I All sixteen registers (see although not all bits are implemented. The fi ...
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... DAYS ( YEARS (0 to 99) AE_M MINUTE_ALARM (0 to 59) AE_H - HOUR_ALARM (0 to 23) AE_D - DAY_ALARM (1 to 31) AE_W - - TIMER_VALUE Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar TESTC N TI_TP WEEKDAYS MONTH ( WEEKDAY_ALARM - - - - - - AIE TIE ...
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... Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar 8.9) Section 8.11.1) (subject to the status of TIE); Reference Section 8.9 Section 8.10 Section 8 ...
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... The pulse generator for the countdown timer interrupt Table 7). [1] INT operation (bit TI_TP = 1) INT period (s) [ 8192 1 128 Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar TI_TP E.G.AIE TIE 0 1 INT AIE 013aaa087 n > 4096 ...
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... Voltage low detector and clock monitor The PCF8564A has an on-chip voltage low detector. When V (Voltage Low) flag is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by using the interface. Fig 5. PCF8564A_1 Product data sheet ...
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... Register Days Table 12. Bit Symbol DAYS [1] The PCF8564A compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. 8.4.5 Register Weekdays Table 13. Bit Symbol WEEKDAYS ...
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... Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar indicates the century is x indicates the century unused actual month coded in BCD format, see ...
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... When the register Years overflows from 99 to 00, the century bit C in the register Months is toggled. The PCF8564A compensates for leap years by adding a 29th day to February if the year counter contains a value which is divisible by 4, including the year 00. 8.5 Setting and reading the time Figure 6 Fig 6 ...
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... Place value Description ten’s place unit place Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar t < data data data STOP 013aaa215 minute alarm is enabled minute alarm is disabled minute alarm information coded in BCD format © ...
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... BCD format Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar hour alarm is enabled hour alarm is disabled unused hour alarm information coded in BCD format day alarm is enabled day alarm is disabled ...
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... DAY ALARM = DAY TIME WEEKDAY ALARM = WEEKDAY TIME It’s only on increment to a matched case that the alarm flag is set, see Alarm function block diagram Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar example AE_M AE_M AE_H (1) set alarm flag, AF ...
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... CLKOUT 32.768 kHz 1.024 kHz Hz) and enables or disables the timer. The timer 60 Description timer is disabled timer is enabled unused timer source clock frequency select 4.096 kHz PCF8564A [2] © NXP B.V. 2009. All rights reserved ...
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... Timer - timer register (address 0Fh) bit description Value Description CountdownPeriod Timer register bits value range divide chain called a prescaler. The prescaler can be set to a known Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar n = -------------------------------------------------------------- - SourceClockFrequency C-bus clock (SDA) must be © ...
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... Product data sheet OSC STOP DETECTOR STOP bit functional diagram 8192 Hz stop released Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar held in reset and 2 14 Figure 9). The time circuits can then be set and Figure 10 and Table ...
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... The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The uncertainty is caused by the prescaler bits F (see Table 8.11 Reset The PCF8564A includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I all registers are set according to reset. PCF8564A_1 ...
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... Day_alarm 1 x Weekday_alarm 1 x CLKOUT_ctrl 1 x Timer_ctrl 0 x Timer signals on the pins SDA and SCL are toggled as illustrated in 500 ns 2000 ns Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar ...
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... Product data sheet 2 C-bus Figure SDA SCL data line stable; data valid Figure 13. S START condition Figure Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar 12). change of data allowed mbc621 P STOP condition 14). © NXP B.V. 2009. All rights reserved. SDA SCL mbc622 ...
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... TRANSMITTER / RECEIVER RECEIVER 2 C-bus is shown in data output data output by receiver SCL from 1 master S START condition 2 C-bus Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar MASTER MASTER TRANSMITTER / TRANSMITTER RECEIVER mba605 Figure 15. not acknowledge acknowledge clock pulse for acknowledgement © ...
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... Clock and calendar READ or WRITE cycles Figure 17, PCF8564A READ and WRITE cycles. The word address is a 4-bit value that defines which register accessed next. The upper four bits of the word address are not used. Fig 17. Master transmits to slave receiver (WRITE mode) ...
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... Fig 19. Master reads slave immediately after first byte (READ mode) PCF8564A_1 Product data sheet acknowledgement from slave WORD ADDRESS A S SLAVE ADDRESS at this moment master transmitter becomes master receiver and PCF8564A slave receiver becomes slave transmitter acknowledgement from slave SLAVE ADDRESS DATA R/W n bytes Rev. 1 — 8 October 2009 ...
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... HBM MM latch-up current all pins but OSCI storage temperature Ref. 8 “JESD78” = +85 C). Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar CLKOE V DD CLKOUT SCL SDA 013aaa035 Min 0.5 0.5 ...
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... CLKOUT enabled at 32 kHz +85 C amb pins SDA and SCL on pins CLKOE and CLKOUT (test mode) Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar = pF; unless otherwise s L Min Typ Max [1] 1.0 - 5.5 [1] 1.8 - 5.5 ...
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... pin CLKOUT 4 amb = V + 0.3 V. DD(po)min DD(min Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar = pF; unless otherwise s L Min Typ 0. [ 0 ...
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... V (V) DD Fig 22. I mgr890 frequency deviation (ppm) 80 120 Fig 24. Frequency deviation as a function of V Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar timer = 1 minute; CLKOUT = 32 kHz. amb as a function ...
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... 32.768 kHz; quartz R amb osc Conditions V = 200 mV amb [3][4] Figure 25 calculation of C and C OSCI OSCO Ref. 11 “UM10204”. Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar = pF; unless otherwise s L Min Typ [ 0 [ ...
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... BUF LOW t HD;STA C-bus timing waveforms SCL CLOCK/CALENDAR OSCI PCF8564A SDA OSCO V SS Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar HD;DAT t HIGH t SU;STA V DD SDA MASTER TRANSMITTER/ RECEIVER SCL SDA ...
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... Dimensions Die type 2 (3) (1) (1) Unit max mm nom 0.2 1.26 1.89 1.05 0.22 min Note 1. Chip dimensions including sawline. 2. Marking code: PC8564A-1 3. Dimension depending on delivery form Outline version IEC PCF8564AU Fig 27. Bare die outline of PCF8564AU PCF8564A_1 Product data sheet 0,0 ( 0.9 0.1 0.09 0.1 ...
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... All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip; see Symbol OSCI OSCO INT V SS SDA SCL CLKOUT V DD CLKOE PCF8564A_1 Product data sheet Bonding pad description for all PCF8564AU types Figure 27. Pad 523.0 689.4 2 523.0 469.4 3 523.0 429.8 4 523 ...
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... Note 1. Chip dimensions including sawline. 2. Marking code: PC8564A-1 Outline version IEC PCF8564ACX9 Fig 28. Bare die outline of PCF8564ACX9 Table 32. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol OSCI OSCO INT V SS ...
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... NXP Semiconductors Fig 29. Alignment marks of all PCF8564A types Table 33. All x/y coordinates represent the position of the REF point (see (x the chip; see Alignment markers 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A , IEC 61340-5 or equivalent standards ...
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... NXP Semiconductors 18. Packing information 18.1 Wafer and FFC information Marking code Straight edge of the wafer Wafer thickness, see Table Fig 30. Wafer layout of PCF8564AU PCF8564A_1 Product data sheet die type die type die type die type Rev. 1 — 8 October 2009 ...
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... NXP Semiconductors Marking code Straight edge of the wafer Wafer thickness, see Table Fig 31. Wafer layout of PCF8564ACX9 PCF8564A_1 Product data sheet Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar Saw lane Seal ring plus gap to active circuit ~18 m ...
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... NXP Semiconductors 18.2 Tape and reel information Fig 32. Tape and reel details for PCF8564ACX9/B/1 Table 34. Dimension [1] Die is placed in pocket bump side down. Fig 33. Pin 1 indication for PCF8564ACX9/B/1 19. Soldering of WLCSP packages 19.1 Introduction to soldering WLCSP packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 “ ...
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... Product data sheet Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 34. Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar Figure 34) than a PbSn process, thus Table 35. 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar peak temperature time 001aac844 © NXP B.V. 2009. All rights reserved ...
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... To reflow the solder, use the solder profile shown in application note AN10365 “Surface mount reflow soldering description” . 19.3.4 Cleaning Cleaning can be done after reflow soldering. PCF8564A_1 Product data sheet Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar © NXP B.V. 2009. All rights reserved ...
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... Read Only Memory Real Time Clock Serial Clock Line Serial Data Line Static Random Access Memory Wafer Level Chip-Size Package 2 C-bus specification and user manual Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 22. Revision history Table 37. Revision history Document ID Release date PCF8564A_1 20091008 PCF8564A_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar Supersedes - © NXP B.V. 2009. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 1 — 8 October 2009 PCF8564A Real time clock and calendar © NXP B.V. 2009. All rights reserved ...
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... Introduction to soldering WLCSP packages Board mounting . . . . . . . . . . . . . . . . . . . . . . . 38 Reflow soldering Stand off Quality of solder joint . . . . . . . . . . . . . . . . . . . 39 Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Revision history . . . . . . . . . . . . . . . . . . . . . . . 42 Legal information . . . . . . . . . . . . . . . . . . . . . . 43 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Contact information . . . . . . . . . . . . . . . . . . . . 43 Contents Date of release: 8 October 2009 Document identifier: PCF8564A_1 All rights reserved. ...