PCF2127AT/1,518 NXP Semiconductors, PCF2127AT/1,518 Datasheet
PCF2127AT/1,518
Specifications of PCF2127AT/1,518
Related parts for PCF2127AT/1,518
PCF2127AT/1,518 Summary of contents
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PCF2127A Integrated RTC, TCXO and quartz crystal Rev. 02 — 7 May 2010 1. General description The PCF2127A is a CMOS Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal optimized for very high accuracy and very ...
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... NXP Semiconductors Automatic leap year correction 3. Applications Electronic metering for electricity, water, and gas Timekeeping instruments with high precision GPS equipment to reduce time to first fix Applications that require an accurate process timing Products with long automated unattended operation time 4. Ordering information Table 1. ...
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... NXP Semiconductors 6. Block diagram CLKOUT BBS V DD BATTERY BACK UP V SWITCH-OVER BAT CIRCUITRY V SS OSCILLATOR MONITOR RST INTERFACE SDA/CE SERIAL BUS SDO INTERFACE SDI SELECTOR SCL IFS INTERFACE TS PFI 1.25 V (internal) PFO Fig 1. Block diagram of PCF2127A PCF2127A_2 Product data sheet TCXO OSCI 32 ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. 7.2 Pin description Table 3. Symbol SCL SDI SDO SDA/CE IFS TS CLKOUT V SS n.c. TEST PFO PFI RST INT BBS V BAT V DD PCF2127A_2 Product data sheet SCL 1 SDI 2 3 SDO 4 SDA/CE IFS CLKOUT n.c. n.c. ...
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... NXP Semiconductors 8. Functional description The PCF2127A is a Real Time Clock (RTC) and calendar with an on-chip Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated into the same package. Address and data are transferred by a selectable 400 kHz Fast-mode I SPI-bus with separate data input and output (see SPI-bus is 6 ...
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... NXP Semiconductors 8.1 Register overview The PCF2127A contains 30 8-bit registers (see address register: the built-in address register will increment automatically after each read or write of a data byte up to the register 1Bh. After register 1Bh the auto-incrementing will wrap around to address 00h. The registers 1Ch and 1Dh must be addressed directly (see Figure 3) ...
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... NXP Semiconductors • Address registers 1Ah and 1Bh define the RAM address. Address register 1Ch (RAM_wrt_cmd) is the RAM write command; address register 1Dh (RAM_rd_cmd) is the RAM read command. Data is transferred to or from the RAM via the serial interface (see • The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded in Binary Coded Decimal (BCD) format to simplify application use ...
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... NXP Semiconductors Table 4. Register overview …continued Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit 7 14h Min_timestp - 15h ...
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... NXP Semiconductors 8.2 Control registers PCF2127A has 30 8-bit registers. The first 3 registers with the addresses 00h, 01h, and 02h are used as control registers. 8.2.1 Register Control_1 Table 5. Bit [1] Default value. [2] When writing to the register this bit has always to be set logic 0. ...
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... NXP Semiconductors 8.2.2 Register Control_2 Table 6. Bit [1] Default value. PCF2127A_2 Product data sheet Control_2 - control and status register 2 (address 01h) bit description Symbol Value Description [1] MSF 0 no minute or second interrupt generated 1 flag set when minute or second interrupt generated; flag must be cleared to clear interrupt ...
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... NXP Semiconductors 8.2.3 Register Control_3 Table 7. Bit PWRMNG[2: [1] Values see [2] Default value. PCF2127A_2 Product data sheet Control_3 - control and status register 3 (address 02h) bit description Symbol Value Description [1] control of the battery switch-over, battery low detection, and extra power fail detection functions ...
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... NXP Semiconductors 8.3 Register CLKOUT_ctl Table 8. Bit Symbol TCR[1: COF[2:0] 8.3.1 Temperature compensated crystal oscillator The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the PCF2127A the frequency drift caused by temperature variation is corrected by adjusting the load capacitance of the crystal oscillator. The load capacitance is changed by switching between two load capacitance values using a modulation signal with a programmable duty cycle ...
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... NXP Semiconductors Table 10. COF[2:0] [2] 000 001 010 011 100 101 110 111 [1] Duty cycle definition: % HIGH-level time : % LOW-level time. [2] Default value. PCF2127A_2 Product data sheet CLKOUT frequency selection CLKOUT frequency (Hz) 32768 16384 8192 4096 2048 1024 1 CLKOUT = high-Z All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 8.4 Register Aging_offset Table 11. Bit Symbol AO[3:0] 8.4.1 Crystal aging correction The PCF2127A has an aging offset register Aging_offset to correct the crystal aging 2 effects The accuracy of the frequency of a quartz crystal depends on the aging. Crystal suppliers usually specify the first year aging (typically ±1 ppm, maximum ±3 ppm) and/or the 10 years aging (typically ± ...
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... NXP Semiconductors 8.5 General purpose 512 bytes static RAM The PCF2127A contains a general purpose 512 bytes static RAM. This integrated SRAM is battery backed and can therefore be used to store data which is essential for the application to survive a power outage. 9 bits, RA[8:0], define the RAM address pointer in registers RAM_addr_MSB and RAM_addr_LSB ...
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... NXP Semiconductors 8.5.5 Operation examples Writing to the RAM 8.5.5.1 1. Set RAM address: – Select register RAM_addr_MSB (send address 1Ah). – Set value for bit RA8 (data byte of register 1Ah). Note: register address will be incremented automatically to 1Bh. – Set value for array RA[7:0] (data byte of register 1Bh). ...
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... NXP Semiconductors 8.6 Power management functions The PCF2127A has two power supply pins and one power output pin: • • V BAT • BBS - battery backed output voltage pin (equal to the internal power supply) The PCF2127A has three power management functions implemented: • ...
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... NXP Semiconductors 8.6.1 Battery switch-over function The PCF2127A has a backup battery switch-over circuit which monitors the main power supply V condition is detected. One of two operation modes can be selected: • Standard mode: the power failure condition happens when • Direct switching mode: the power failure condition happens when V ...
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... NXP Semiconductors V V th(sw)bat (= 2 Fig 4. 8.6.1.2 Direct switching mode If V > < th(sw)bat (= 2 Fig 5. PCF2127A_2 Product data sheet backup battery operation BBS BAT BF INT Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled) the internal power supply is V BAT the internal power supply is V ...
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... NXP Semiconductors The direct switching mode is useful in systems where V The direct switching mode is not recommended if the V (e. reduced compared to the standard mode because the monitoring of V not performed. 8.6.1.3 Battery switch-over disabled: only one power supply (V When the battery switch-over function is disabled: • ...
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... NXP Semiconductors V BBS (mV) Fig 7. 8.6.3 Battery low detection function The PCF2127A has a battery low detection circuit which monitors the status of the battery V . BAT When V (register Control_3) is set to indicate that the battery is low and that it must be replaced. Monitoring of the battery voltage also occurs during battery operation. ...
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... NXP Semiconductors th(bat)low (= 2.5 V) Fig 8. 8.6.4 Extra power fail detection function The PCF2127A has an extra power fail detection circuit which compares the voltage at the power fail input pin PFI to an internal reference voltage equal to 1. < 1.25 V the power fail output PFO is driven LOW. PFO is an open-drain, active PFI LOW output which requires an external pull-up resistor in any application ...
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... NXP Semiconductors uvp V th(uvp) below the minimum operating voltage of the system, in order to allow the microcontroller to perform early backup operations. If the extra power fail detection function is not used, pin PFI must be connected to V pin PFO must be left open circuit. 8.6.4.1 Extra power fail detection when the battery switch over function is enabled • ...
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... NXP Semiconductors th(uvp) V th(sw)bat (= 2 comparator enabled PF0 Fig 11. PFO signal behavior when battery switch-over is enabled in direct switching 8.6.4.2 Extra power fail detection when the battery switch-over function is disabled If the battery switch-over function is disabled and the power fail comparator is enabled, the power fail output at pin PFO depends only on the result of the comparison between V and 1 ...
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... NXP Semiconductors 8.7 Oscillator stop detection function The PCF2127A has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF (in register Seconds) is set logic 1. • Power-on: a. The oscillator is not running, the chip is in reset (pin RST is LOW and flag OSF is logic 1) ...
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... NXP Semiconductors 8.8 Reset function The PCF2127A has an active LOW open-drain output reset pin (RST). The reset output is activated at Power-On Reset (POR) and whenever the oscillator is stopped (see Section 8.8.1 Power-On Reset (POR) The POR is active whenever the oscillator is stopped. The oscillator is also considered to ...
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... NXP Semiconductors Fig 15. Power-On Reset (POR) system The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 16. All timings shown are required minimum. SDA/CE reset override Fig 16 ...
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... NXP Semiconductors 8.9 Time and date function The majority of these registers are coded in the Binary Coded Decimal (BCD) format. 8.9.1 Register Seconds Table 19. Bit Symbol 7 OSF SECONDS [1] Start-up value. Table 20. Seconds value in decimal 8.9.2 Register Minutes Table 21. Bit Symbol MINUTES PCF2127A_2 ...
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... NXP Semiconductors 8.9.3 Register Hours Table 22. Bit Symbol hour mode 5 AMPM 4 HOURS hour mode HOURS [1] Hour mode is set by the bit 12_24 in register Control_1. 8.9.4 Register Days Table 23. Bit Symbol DAYS [1] The RTC compensates for leap years by adding a 29 which is exactly divisible by 4, including the year 00. ...
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... NXP Semiconductors 8.9.6 Register Months Table 26. Bit Symbol MONTHS Table 27. Month January February March April May June July August September October November December 8.9.7 Register Years Table 28. Bit Symbol YEARS 8.9.8 Setting and reading the time Figure 17 During read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked ...
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... NXP Semiconductors Fig 17. Data flow of the time function After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Fig 18 ...
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... NXP Semiconductors 8.10 Alarm function When one or more of the alarm bit fields are loaded with a valid second, minute, hour, day, or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information is compared with the actual second, minute, hour, day, and weekday (see (1) Only when all enabled alarm settings are matching ...
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... NXP Semiconductors 8.10.2 Register Minute_alarm Table 30. Bit Symbol 7 AE_M MINUTE_ALARM [1] Default value. 8.10.3 Register Hour_alarm Table 31. Bit Symbol 7 AE_H hour mode 5 AMPM 4 HOUR_ALARM hour mode HOUR_ALARM [1] Default value. [2] Hour mode is set by the bit 12_24 in register Control_1. 8.10.4 Register Day_alarm Table 32. ...
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... NXP Semiconductors 8.10.5 Register Weekday_alarm Table 33. Bit Symbol 7 AE_W WEEKDAY_ALARM [1] Default value. 8.10.6 Alarm flag When all enabled comparisons first match, the alarm flag AF (register Control_2) is set. AF will remain set until cleared by using the interface. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. For clearing the flags see Alarm registers which have their alarm enable bit AE_x at logic 1 are ignored ...
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... NXP Semiconductors 8.11 Timer functions The PCF2127A has two different timer functions, a watchdog timer and a countdown timer. The timers can be selected by using the control bits WD_CD[1:0] in the register Watchdg_tim_ctl. • The watchdog timer has four selectable source clocks. It can, for example, be used to ...
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... NXP Semiconductors 8.11.2 Register Watchdg_tim_val Table 35. Bit WATCHDG_TIM_VAL[7:0] Table 36. TF[1:0] Timer source 8.11.3 Watchdog timer function The watchdog timer function is controlled by the WD_CD[1:0] bits of the register Watchdg_tim_ctl (see The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or ...
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... NXP Semiconductors Remark: WDTF is read only and cannot be cleared with the interface. WDTF can be cleared by: • loading a value in register Watchdg_tim_val • reading of the register Control_2 Writing a logic 0 or logic 1 to WDTF has no effect. watchdog timer value WDTF Fig 21. WD_CD[1:0] = 10: watchdog activates an interrupt when timed out • ...
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... NXP Semiconductors Table 37. WD_CD[1:0] 11 8.11.4 Countdown timer function The countdown timer function is controlled by the WD_CD[1:0] bits in register Watchdg_tim_ctl (see The timer counts down from the software programmed 8 bit binary value n in register Watchdg_tim_val. When the counter reaches 1 • the countdown timer flag CDTF is set • ...
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... NXP Semiconductors When the countdown timer flag CDTF is set, an interrupt signal on INT will be generated provided that this mode is enabled. See be controlled. When starting the countdown timer for the first time, only the first period will not have a fixed duration. The amount of inaccuracy for the first timer period will depend on the chosen source clock, see Table 38 ...
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... NXP Semiconductors Table 40. Register Control_2 The following tables show what instruction must be sent to clear the appropriate flag. Table 41. Register Control_2 [1] The bits labeled as - have to be rewritten with the previous values. Table 42. Register Control_2 [1] The bits labeled as - have to be rewritten with the previous values. ...
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... NXP Semiconductors 8.12 Timestamp function The PCF2127A has an active LOW timestamp input pin TS, internally pulled with an on-chip pull-up resistor to the internal power supply of the device. It also has a timestamp detection circuit which can detect two different events: 1. Input on pin TS is driven to an intermediate level between power supply and ground. ...
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... NXP Semiconductors The TSF1 and TSF2 flags can be cleared by using the interface; clearing both flags will clear the interrupt. Once TSF2 is cleared it will only be set again when TS pin is driven to ground once again. 8.12.2 Time stamp mode The timestamp function has two different modes selected by the control bit TSM (timestamp mode) in register Timestp_ctl: • ...
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... NXP Semiconductors 8.12.3.4 Register Hour_timestp Table 48. Bit Symbol hour mode 5 AMPM 4 HOUR_TIMESTP hour mode HOUR_TIMESTP [1] Hour mode is set by the bit 12_24 in register Control_1. 8.12.3.5 Register Day_timestp Table 49. Bit Symbol DAY_TIMESTP 8.12.3.6 Register Mon_timestp Table 50. Bit Symbol MONTH_TIMESTP 8.12.3.7 Register Year_timestp Table 51. ...
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... NXP Semiconductors 8.12.4 Dependency between Battery switch-over and timestamp The timestamp function depends on the control bit BTSE in register Control_3: Table 52. BTSE [1] Default value. PCF2127A_2 Product data sheet Battery switch-over and timestamp Description [1] - the battery switch-over does not affect the timestamp registers ...
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... NXP Semiconductors 8.13 Interrupt output, INT SECONDS COUNTER MINUTES COUNTER from interface: clear MSF WD_CD[1: COUNTDOWN COUNTER from interface: clear CDTF WD_CD[1: WATCHDOG COUNTER MCU loading watchdog counter set alarm flag, AF from interface: clear AF set timestamp flag, TSFx from interface: clear TSFx ...
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... NXP Semiconductors • watchdog timer • alarm • timestamp • battery switch-over • battery low detection The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the interrupts generated from the second/minute timer (flag MSF in register Control_2) and the countdown timer (flag CDTF in register Control_2) are pulsed signals or a permanently active signal ...
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... NXP Semiconductors INT when only MI enabled MSF when only MI enabled Fig 26. INT example for SI and MI when TI_TP is logic 1 Fig 27. INT example for SI and MI when TI_TP is logic 0 The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and generates a pulse of 8 ...
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... NXP Semiconductors 8.13.3 INT pulse shortening The pulse generator for the countdown timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the countdown timer and on the countdown value consequence, the width of the interrupt pulse varies (see Table 54) ...
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... NXP Semiconductors (1) Indicates normal duration of INT pulse. Fig 29. Example of shortening the INT pulse by clearing the CDTF flag 8.13.4 Watchdog timer interrupts The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0] bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows the status of the watchdog timer flag WDTF (register Control_2) ...
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... NXP Semiconductors 8.13.6 Timestamp interrupts Interrupt generation from the timestamp function is controlled using the TSIE bit (register Control_2). If TSIE is enabled the INT pin follows the status of the flags TSFx. Clearing the flags TSFx immediately clears INT. No pulse generation is possible for timestamp interrupts ...
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... NXP Semiconductors 8.14 External clock test mode A test mode is available which allows on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz) with the signal applied to pin CLKOUT ...
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... NXP Semiconductors 8.15 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. STOP will cause the upper part of the prescaler (F are generated. The time circuits can then be set and will not increment until the STOP bit is released ...
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... NXP Semiconductors 32768 Hz F OSC Fig 31. STOP bit functional diagram Fig 32. STOP bit release timing PCF2127A_2 Product data sheet LOWER PRESCALER 128 Hz 16384 Hz 8192 Hz 4096 stop released All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 Integrated RTC, TCXO and quartz crystal ...
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... NXP Semiconductors 9. Interfaces The PCF2127A has a selectable I the interface selection pin IFS (see Table 56. Pin IFS V DD SCL SDI SDO CE SCL 1 SDI 2 SDO 3 SDA/CE 4 IFS 5 PCF2127A select the SPI-bus interface, pin IFS has to be connected to pin SPI-bus interface selection Fig 33. Interface selection ...
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... NXP Semiconductors 9.1 SPI-bus interface Data transfer to and from the device is made via a 3 wire SPI-bus (see lines for input and output are split. The data input and output line can be connected together to facilitate a bidirectional data bus (see whenever the chip enable line pin SDA/CE is inactive. ...
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... NXP Semiconductors Table 58. Bit R SCL SDI SDA/CE address xx counter In this example, the register Seconds is set to 45 seconds and the register Minutes to 10 minutes. Fig 36. SPI-bus write example R SCL SDI SDO SDA/CE address xx counter In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this configuration important that pin SDI is never left floating ...
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... NXP Semiconductors 2 9.2 I C-bus interface 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER RECEIVER Fig 40. System configuration 9.2.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • ...
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... NXP Semiconductors Table 59. Bit The R/W bit defines the direction of the following single or multiple byte data transfer (read is logic 1, write is logic 0). For the format and the timing of the START condition (S), the STOP condition (P), and the acknowledge bit (A) refer to the I characteristics table either a STOP condition or the START condition of the next data transfer ...
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... NXP Semiconductors S P/S Fig 44. Bus protocol, writing to RAM PCF2127A_2 Product data sheet acknowledge from PCF2127A slave address write bit acknowledge from PCF2127A data byte 1Ah A acknowledge from PCF2127A slave address write bit acknowledge from PCF2127A data byte (RAM address data bytes All information provided in this document is subject to legal disclaimers. Rev. 02 — ...
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... NXP Semiconductors S P/S P/S Fig 45. Bus protocol, reading from RAM PCF2127A_2 Product data sheet acknowledge from PCF2127A slave address write bit acknowledge from PCF2127A data byte 1Ah A acknowledge from PCF2127A slave address write bit acknowledge from PCF2127A slave address read bit ...
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... NXP Semiconductors 10. Internal circuitry Fig 46. Device diode protection diagram of PCF2127A PCF2127A_2 Product data sheet SCL SDI SDO SDA/CE IFS TS CLKOUT V SS PCF2127A All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 PCF2127A Integrated RTC, TCXO and quartz crystal ...
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... NXP Semiconductors 11. Limiting values Table 60. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol BAT P tot V ESD stg T oper [1] Pass level; Human Body Model (HBM) according to [2] Pass level; Machine Model (MM), according to [3] Pass level; Charged-Device Model (CDM), according to [4] Pass level ...
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... NXP Semiconductors 12. Static characteristics Table 61. Static characteristics Symbol Parameter Supplies V supply voltage DD V battery supply voltage BAT V calibration supply voltage DD(cal) V low voltage low I supply current DD I battery supply current BAT Power management V battery switch threshold th(sw)bat voltage V low battery threshold voltage ...
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... NXP Semiconductors Table 61. Static characteristics Symbol Parameter Inputs V input voltage I V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI C input capacitance i Outputs V output voltage O I LOW-level output current OL I HIGH-level output current OH I output leakage current ...
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... NXP Semiconductors 12.1 Current consumption characteristics, typical Fig 47. I (μA) Fig 48. I PCF2127A_2 Product data sheet (mA 1.5 Typical value 0 pin SDA/ 1.6 1.2 0.8 0.4 0 −40 −20 0 CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating function of temperature DD All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors (μA) a. PWRMNG[2:0] = 111; TSOFF = 1; T (μA) b. PWRMNG[2:0] = 000; TSOFF = 0; T Fig 49. I PCF2127A_2 Product data sheet 2 1.6 1.2 0.8 0.4 0 1.8 2.2 2.6 4 3.2 2.4 1.6 0.8 0 1.8 2.2 2 function All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 ...
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... NXP Semiconductors 12.2 Frequency characteristics Table 62. Frequency characteristics Symbol Parameter f output frequency o Δf/f frequency stability Δf /f relative crystal frequency variation xtal xtal Δf/ΔV frequency variation with voltage ±1 ppm corresponds to a time deviation of ±0.0864 seconds per day. [1] [2] Not production tested. Effects of reflow solder not included (see ...
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... NXP Semiconductors 13. Dynamic characteristics 13.1 SPI-bus timing characteristics Table 63. SPI-bus characteristics 4.2V operating supply voltage at ambient temperature and referenced to V Symbol Parameter Pin SCL f SCL clock frequency clk(SCL) t SCL time SCL t clock HIGH time clk(H) t clock LOW time clk(L) t rise time ...
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... NXP Semiconductors CE t su(CE_N) SCL WRITE SDI R/W SA2 high-Z SDO READ SDI b7 high-Z SDO Fig 51. SPI-bus timing PCF2127A_2 Product data sheet t w(CE_N 80% 20% RA0 t(SDI-SDO) All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 PCF2127A Integrated RTC, TCXO and quartz crystal ...
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... NXP Semiconductors 2 13 interface timing characteristics Table 64. All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference and 70 % with an input voltage swing of V Symbol Parameter Pin SCL f SCL t LOW t HIGH Pin SDA/CE t SU;DAT t HD;DAT Pins SCL and SDA/CE ...
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... NXP Semiconductors START PROTOCOL CONDITION (S) t SU;STA SCL t BUF SDA t HD;STA 2 Fig 52. I C-bus timing diagram; rise and fall times refer and 70 % 14. Application information For information about application configuration see PCF2127A_2 Product data sheet BIT 7 BIT 6 MSB (A6) (A7 LOW HIGH ...
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... NXP Semiconductors 15. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 16. Soldering For information about soldering see 17. Abbreviations Table 65. Acronym AM BCD CDM CMOS DC GPS HBM LSB MCU MM MSB PM POR PORO PPM RAM RC RTC SCL SDA SPI SRAM TCXO Xtal PCF2127A_2 Product data sheet Ref. 3 Abbreviations Description Ante Meridiem Binary Coded Decimal ...
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... NXP Semiconductors 18. References [1] AN10365 — Surface mount reflow soldering description [2] AN10853 — Handling precautions of ESD sensitive devices [3] AN10857 — Application and soldering information for PCF2127A and PCF2129A TCXO RTC [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous ...
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... Revision history Document ID Release date PCF2127A_2 20100507 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Adjusted I PCF2127A_1 20100121 PCF2127A_2 ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: PCF2127A_2 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 5 8.1 Register overview . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9 8.2.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 10 8 ...
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... NXP Semiconductors 9 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 55 9.1.1 Data transmission . . . . . . . . . . . . . . . . . . . . . . 55 2 9.2 I C-bus interface 9.2.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.2 START and STOP conditions . . . . . . . . . . . . . 57 9.2.3 System configuration . . . . . . . . . . . . . . . . . . . 57 9.2.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 58 2 9.2.5 I C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 58 10 Internal circuitry Limiting values Static characteristics 12.1 Current consumption characteristics, typical . 66 12 ...