PCF2127AT/1,518 NXP Semiconductors, PCF2127AT/1,518 Datasheet - Page 48

• Manufacturer Part Number: PCF2127AT/1,518
• Description: IC RTC/CALENDAR TCXO QTZ 20SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2127AT/1,518

• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Time Format: HH:MM:SS (12/24 hr)
• Memory Size: 512B
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 4.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Serial Clock, Timestamp, Timekeeper, Watchdog, Alarm, Calendar, Timer, Timer Interrupt
• Rtc Memory Size: 512 bytes
• Supply Voltage (max): 4.2 V
• Supply Voltage (min): 1.8 V
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 2600 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PCF2127A_2
Product data sheet
8.13.3 INT pulse shortening
The pulse generator for the countdown timer interrupt also uses an internal clock, but this
time it is dependent on the selected source clock for the countdown timer and on the
countdown value n. As a consequence, the width of the interrupt pulse varies (see
Table
Table 54.
[1]
If the MSF or CDTF flag (register Control_2) is cleared before the end of the INT pulse,
then the INT pulse is shortened. This allows the source of a system interrupt to be cleared
immediately when it is serviced, i.e. the system does not have to wait for the completion of
the pulse before continuing; see
and bit CDTF can be found in
Source clock (Hz)
4096
64
1
1
⁄
Fig 28. Example of shortening the INT pulse by clearing the MSF flag
60
n = loaded countdown value. Timer stopped when n = 0.
(1) Indicates normal duration of INT pulse.
54).
The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, i.e. when
TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0.
INT operation (bit TI_TP = 1)
seconds counter
All information provided in this document is subject to legal disclaimers.
instruction
MSF
SCL
INT
Rev. 02 — 7 May 2010
58
Section
INT period (s)
n = 1
1
1
1
1
⁄
⁄
⁄
⁄
8192
128
64
64
Figure 28
59
[1]
8.11.6.
CLEAR INSTRUCTION
and
Integrated RTC, TCXO and quartz crystal
Figure
29. Instructions for clearing bit MSF
8th clock
n > 1
1
1
1
1
⁄
⁄
⁄
⁄
4096
64
64
64
PCF2127A
001aaf908
© NXP B.V. 2010. All rights reserved.
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