ISL12022IBZ-T7A Intersil, ISL12022IBZ-T7A Datasheet - Page 19

• Manufacturer Part Number: ISL12022IBZ-T7A
• Description: IC RTC/CALENDAR TEMP SNSR 8SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022IBZ-T7A

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ALARM Registers (10h to 15h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the alarm
registers and the RTC registers. As the RTC advances, the
alarm will be triggered once a match occurs between the
alarm registers and the RTC registers. Any one alarm register,
multiple registers, or all registers can be enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
• Single Event Mode is enabled by setting the bit 7 on any
• Interrupt Mode is enabled by setting the bit 7 on any of
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL
of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit
to “0”, and disabling the frequency output. This mode
permits a one-time match between the Alarm registers
and the RTC registers. Once this match occurs, the ALM
bit is set to “1” and the IRQ/F
and will remain low until the ALM bit is reset. This can be
done manually or by using the auto-reset feature.
the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to
“1”, and disabling the frequency output. The IRQ/F
FDTR<2:0>
00100
00101
01000
01001
01010
10000
10001
10010
10100
10101
00011
00110
00111
10011
10110
10111
11000
11001
11010
DIGITAL TRIMMING REGISTER (Continued)
DECIMAL
19
-10
10
-1
-2
-3
-4
-5
-6
-7
-8
-9
3
4
5
6
7
8
9
0
OUT
output will be pulled low
ADJUSTMENT
-152.5
-213.5
-274.5
152.5
213.5
274.5
-30.5
-91.5
ppm
-122
-183
-244
-305
91.5
122
183
244
305
-61
0
OUT
ISL12022
To clear a single event alarm, the ALM bit in the status
register must be set to “0” with a write. Note that if the ARST
bit is set to 1 (address 08h, bit 7), the ALM bit will
automatically be cleared when the status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
• Alarm set with single interrupt (IM = ”0”)
• A single alarm will occur on January 1 at 11:30 a.m.
• Set Alarm registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ/F
low.
Example 2
• Pulsed interrupt once per minute (IM = ”1”)
• Interrupts at one minute intervals when the seconds
• Set Alarm registers as follows:
REGISTER
REGISTER
ALARM
output will now be pulsed each time an alarm occurs. This
means that once the interrupt mode alarm is set, it will
continue to alarm for each occurring match of the alarm
and present time. This mode is convenient for hourly or
daily hardware interrupts in microcontroller applications
such as security cameras or utility meter reading.
register is at 30s.
ALARM
MNA0
MOA0
DWA0
HRA0
DWA0
SCA0
DTA0
MNA0
MOA0
SCA0
HRA0
DTA0
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0 HEX
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
0 0 0 0 0 0 0 0 00h Minutes disabled
0 0 0 0 0 0 0 0 00h Hours disabled
0 0 0 0 0 0 0 0 00h Date disabled
0 0 0 0 0 0 0 0 00h Month disabled
0 0 0 0 0 0 0 0 00h Day of week disabled
BIT
BIT
00h Seconds disabled
B0h Minutes set to 30,
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
enabled
DESCRIPTION
enabled
enabled
enabled
enabled
disabled
DESCRIPTION
OUT
June 23, 2009
output
FN6659.2