XC3S50AN-5FTG256C Xilinx Inc, XC3S50AN-5FTG256C Datasheet
XC3S50AN-5FTG256C
Specifications of XC3S50AN-5FTG256C
Available stocks
Related parts for XC3S50AN-5FTG256C
XC3S50AN-5FTG256C Summary of contents
Page 1
Spartan-3AN FPGA In-System Flash User Guide For Spartan®-3AN FPGA applications that read or write data to or from the In-System Flash memory after configuration UG333 (v2.1) January 15, 2009 R ...
Page 2
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
Page 3
Table of Contents Chapter 1: Overview and SPI_ACCESS Interface In-System Flash Summary Accessing In-System Flash Memory After Configuration SPI_ACCESS Design Primitive . . . . . . . . . . . . . . . . . . . ...
Page 4
Auto Page Rewrite Chapter 5: Erase Commands Sector Protect and Sector Lockdown Prevent Erase Operations Erased State . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
R Chapter 9: Security Register Security Register Security Register Program Security Register Read Appendix A: Optional Power-of-2 Addressing Mode How to Determine the Current Addressing Mode Permanently Changing to the Power-of-2 Addressing Mode Power-of-2 Addressing Mode Power-of-2 Addressing . . ...
Page 6
Spartan-3AN In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
Page 7
R Overview and SPI_ACCESS Interface Note: This user guide only applies to Spartan system Flash after configuration. This user guide is not required for applications that only use the in- system Flash to configure the FPGA. For Spartan-3AN FPGA configuration ...
Page 8
Chapter 1: Overview and SPI_ACCESS Interface Table 1-1: In-System Flash Memory Summary Description In-System Flash (ISF) memory bits SRAM page buffers Default Addressing Mode page size (bytes) Optional Power-of-2 Addressing Mode Pages Blocks Sectors Pages per Block Pages per Sector ...
Page 9
R Accessing In-System Flash Memory After Configuration SPI_ACCESS Design Primitive After the FPGA configures, the application loaded into the FPGA can access the ISF memory using a special design primitive called SPI_ACCESS, shown in data accesses to and from the ...
Page 10
Chapter 1: Overview and SPI_ACCESS Interface Table 1-3: SPI_ACCESS Primitive Attributes (Continued) Attribute Type Allowed Values SIM_MEM_FILE String Specified file and directory name SIM_FACTORY_ID 64-byte Any 64-byte Hex Hex Value Value SIM_DELAY_TYPE String “ACCURATE”, “SCALED” HDL Instantiation Examples The SPI_ACCESS ...
Page 11
R CSB CLK ); -- End of SPI_ACCESS_inst instantiation Verilog Using Verilog, simply connect the SPI_ACCESS design primitive to signal names within the FPGA application. SPI_ACCESS #( .SIM_DEVICE("3S700AN") ) SPI_ACCESS_inst ( .MISO(MISO_signal), .MOSI(MOSI_signal), .CSB(CSB_signal), .CLK(CLK_signal End of SPI_ACCESS_inst ...
Page 12
Chapter 1: Overview and SPI_ACCESS Interface • The FPGA application selects the ISF memory by driving the SPI_ACCESS CSB input Low when the CLK input is High and de-selects the ISF memory by driving the CSB input High. • When ...
Page 13
R 1. The FPGA application starts the command by driving the SPI_ACCESS CSB input Low, while the CLK input is High. Subsequently, the CSB input must remain Low throughout the entire transfer. 2. The Status Register Read mentioned in Consequently, ...
Page 14
Chapter 1: Overview and SPI_ACCESS Interface Table 1-4: SPI_ACCESS Simulation Supported Commands (Continued) Command Common Application Buffer to Page First erases selected memory page and programs page with data from Program with Built- designated buffer in Erase Buffer to Page ...
Page 15
... Page. Page size depends on both the device and the addressing mode. The one or two SRAM page buffers simplify system interfaces and data programming. All Spartan-3AN FPGAs, except the XC3S50AN FPGA, have two SRAM page buffers. The XC3S50AN FPGA has a single such buffer. ...
Page 16
... Sectors. A sector typically consists of 256 contiguous pages or 32 contiguous blocks, except on the XC3S50AN, which has 128 pages per sector. Sectors have additional control options. Sectors can be selectively write-protected by the FPGA application, a featured called ...
Page 17
R Sector 0 is further subdivided into two, individually protected sub-sectors, as shown in Figure 2-3. While the combined Sector 0 is the same size as all other sectors, Sector 0a is always 8 pages while Sector 0b represents the ...
Page 18
Chapter 2: In-System Flash Memory Architecture • Counters, to track the number of program/erase cycles per page. Sector Address Block Address Page Address Figure 2-4: Default Addressing Mode for ...
Page 19
R Default Addressing Mode In the default addressing mode, specific memory bytes are addressed by page and by the specific byte location within that page. As shown in page size varies by FPGA part number. Table 2-2: Default Addressing Mode ...
Page 20
... Consequently, the starting page number is different between the addressing modes for any user data that shares a sector with the end of an FPGA configuration bitstream. • ISF memory allocation for the XC3S50AN FPGA is provided in • ISF memory allocation for the XC3S200AN FPGA is provided in • ...
Page 21
... R Table 2-3: XC3S50AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data space Second available user data space (page aligned) Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 ...
Page 22
Chapter 2: In-System Flash Memory Architecture Table 2-4: XC3S200AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data Second available user data space (page aligned) User data space ...
Page 23
R Table 2-5: XC3S400AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data Second available user data space (page aligned) Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) ...
Page 24
Chapter 2: In-System Flash Memory Architecture Table 2-6: XC3S700AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data Second available user data space (page aligned) User data space ...
Page 25
R Table 2-7: XC3S1400AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data Second available user data space (page aligned) User data space (sector aligned) Spartan-3AN FPGA In-System ...
Page 26
Chapter 2: In-System Flash Memory Architecture MultiBoot Configuration Bitstream Guidelines The following guidelines are recommended when storing multiple configuration files in the In-System Flash (ISF) memory. Align to Flash Sector Boundaries Spartan-3AN FPGA MultiBoot addressing is flexible enough to allow ...
Page 27
R User Data Storage Guidelines The following guidelines are recommended when storing user data in the In-System Flash (ISF) memory not intermix user data with the last page of FPGA configuration bitstream data. Intermixing user data and configuration ...
Page 28
Chapter 2: In-System Flash Memory Architecture 28 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
Page 29
... SRAM page buffer (Low Freq) Notes: 1. The Buffer 2 commands are not available in the XC3S50AN because it has only one SRAM page buffer. Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 ® -3AN FPGA application reads In-System Flash (ISF) memory data either ...
Page 30
Chapter 3: Read Commands Fast Read The Fast Read command is best for longer, sequential read operations. This is the same command that the FPGA issues during configuration. This command is also best for code shadowing applications, where the FPGA ...
Page 31
R • Similarly, serially clock in a 24-bit page and byte starting address. ♦ The starting byte location can be anywhere in the ISF memory array, located on any page, as shown in ♦ If using default addressing, see ♦ ...
Page 32
Chapter 3: Read Commands To perform a Random Read command, summarized in Figure 3-3, the FPGA application must perform the following actions. Table 3-3: Random Read (0x03) Command Summary 24-bit Starting Page and Byte Address Command High Address Pin Byte ...
Page 33
... Figure (0x53) Entire contents of selected ISF page are copied to specified buffer SPI_ACCESS Buffer 2 not Status Register available on 7 XC3S50AN READY/BUSY 0 = Page transfer in progress (0x55 Data available in page buffer Figure 3-4: Page to Buffer Transfer Command Table 3-4, most-significant bit first. www.xilinx.com Page to Buffer Transfer 3-4. The contents of the ISF = 400 μ ...
Page 34
... Page to Buffer 2 (1) Transfer 0x55 Notes: 1. The Buffer 2 command is not available in the XC3S50AN because it has only one SRAM page buffer. 2. The Page to Buffer Transfer command is supported in simulation. • Similarly, serially clock in a 24-bit page address. ♦ Only the Page Address is required. Any byte address values are ignored. ...
Page 35
... Buffer 2 Read 0xD6 MISO Notes: 1. The Buffer 2 Read command is not available in the XC3S50AN because it has only one SRAM page buffer. 2. The Buffer Read command (High Frequency) is not supported in simulation. Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 Figure 3-5. The Buffer Read command sequentially The Buffer 2 Read command is not supported on the XC3S50AN FPGA because it (0xD4): 50 MHz maximum, don’ ...
Page 36
... MISO Notes: 1. The Buffer 2 Read command is not available in the XC3S50AN because it has only one SRAM page buffer. 2. The Buffer Read command (Low Frequency) is not supported in simulation possible for the FPGA application to read from one SRAM page buffer while the other ...
Page 37
R ♦ If using the default address scheme, see ♦ If using power-of-2 addressing, see • The slower version of the command while the faster version bits. At this point, the data supplied on the MOSI input does not matter. ...
Page 38
Chapter 3: Read Commands 38 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
Page 39
R Write and Program Commands The Spartan memory either directly to the main Flash memory array or through one of the SRAM page buffers by issuing the appropriate command code. various supported write and program commands. One form is best ...
Page 40
... Buffer 2 operations to a sector Notes: 1. The Buffer 2 commands are not available in the XC3S50AN because it has only one SRAM page buffer. Buffer Write The FPGA application can write data directly to one of the SRAM page buffers. Along with the Buffer Read command, the FPGA application can randomly read or write the buffer data without affecting the ISF memory array ...
Page 41
... Buffer 2 Write 0x87 Notes: 1. The Buffer 2 Write command is not available in the XC3S50AN because it has only one SRAM page buffer. 2. The Buffer Write command is supported in simulation. • Similarly, serially clock in a 24-bit starting byte address. Any page address information is ignored. ♦ ...
Page 42
... Figure 4-2: Buffer to Page Program with Built-in Erase SPI_ACCESS This command will not program a page within a sector that is protected by Sector Protect or Sector Lockdown Buffer 2 not available on XC3S50AN Figure 4-3: Buffer to Page Program without Built-in Erase www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide ...
Page 43
... Buffer 1 to Page Program without Erase 0x88 Buffer 2 to Page Program without Erase 0x89 Notes: 1. The Buffer 2 commands are not available in the XC3S50AN because it has only one SRAM page buffer. 2. The Buffer to Page Program command is supported in simulation. • Similarly, serially clock in a 24-bit page address. ♦ ...
Page 44
... Power-of-2 Addressing: See 0x82 MOSI Page Program (1) Through Buffer 2 0x85 Notes: 1. The Buffer 2 command is not available in the XC3S50AN because it has only one SRAM page buffer. 2. The Page Program Through Buffer command is supported in simulation shown in Table 4-5 and specified in the PP PP Description ...
Page 45
R • Similarly, serially clock in a 24-bit starting page and byte address. ♦ The starting byte location can be anywhere within the selected SRAM page buffer, as shown in ♦ The page address must also be specified. ♦ If ...
Page 46
... Pin Page to Buffer 1 Compare MOSI Page to Buffer 2 Compare Notes: 1. The Buffer 2 command is not available in the XC3S50AN because it has only one SRAM page buffer. 2. The Page to Buffer Compare command is supported in simulation. 46 Figure 4-4, this command compares the contents of the addressed memory Compare ...
Page 47
R • Similarly, serially clock in a 24-bit Page Address. ♦ If using the default address scheme, see ♦ If using power-of-2 addressing, see • To end the command, drive CSB High on the falling edge of CLK. The CSB ...
Page 48
Chapter 4: Write and Program Commands EEPROM-Like, Byte-Level Write Operations The Spartan-3AN FPGA In-System Flash (ISF) memory includes small page size, SRAM page buffers, combined with flexible memory read and write commands. Consequently, the ISF memory can perform small, byte-level ...
Page 49
... Page to Buffer Transfer command followed by a command, as shown in Figure 4-5. (0x58) Updates/rewrites selected page. 1 SPI_ACCESS Buffer 2 not available on XC3S50AN (0x59) Figure 4-5: Auto Page Rewrite Command Table 4-2, most-significant bit first. www.xilinx.com Auto Page Rewrite Buffer to Page Program with PEP Flash Memory Array ...
Page 50
... Auto Page Rewrite (Buffer 1) MOSI Auto Page Rewrite (Buffer 2) Notes: 1. The Buffer 2 command is not available in the XC3S50AN because it has only one SRAM page buffer. 2. The Auto Page Rewrite Through Buffer command is not supported in simulation. • Similarly, serially clock in a 24-bit Page Address. ...
Page 51
R Erase Commands The Spartan operations for maximum application flexibility. • The Page Erase • The Block Erase • The Sector Erase Sector Protect and Sector Lockdown Prevent Erase Operations The Sector Protection erase operations. A page, block, or sector ...
Page 52
Chapter 5: Erase Commands Page Erase The Page Erase command erases any individual page in the ISF memory array, as shown in Figure 5-2. Typically, the Page Erase command is used to prepare a page for a subsequent Buffer to ...
Page 53
... Page Address (2,048 pages Page Address (4,096 pages Page Address (4,096 pages Table 5-4 and specified in the Spartan-3AN FPGA data bit (bit 7) of the Status Register Description Page Erase Time XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN www.xilinx.com Page Erase Table 5 Addressing Mode Power-of-2 Page Size ...
Page 54
Chapter 5: Erase Commands While the Page Erase operation is in progress, the FPGA can access any other portion of the ISF memory, including any of the following commands. • Read from or write to an SRAM page buffer, which ...
Page 55
... If using the default address scheme, see ♦ If using power-of-2 addressing, see • Drive CSB High on the falling edge of CLK to end the command. Table 5-6: Block Addressing Summary FPGA XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 ...
Page 56
... Middle Address Block Address Block Address Block Address 0 0 Block Address Table 5-8 and specified in the READY/BUSY bit (bit 7) of the Description Block Erase Time XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide Low Address Don’t Care bits Don’ ...
Page 57
R Sector Erase The Sector Erase command erases any unprotected, unlocked sector in the main memory, as shown in Sector Erase MOSI MISO CSB CLK To perform a Sector Erase command, the FPGA application must perform the following actions. • ...
Page 58
Chapter 5: Erase Commands ♦ The page address and byte address bits, which follow the Sector Address, specify any valid address location within the sector which erased. ♦ If using the default address scheme, see ♦ If ...
Page 59
... R Table 5-10: Sector Addressing, Default Addressing Mode FPGA / Sector 23 22 XC3S50AN 0 0 Sector Sector 0a Sector 0b Sectors 1– 3 XC3S200AN Sector 0 0 XC3S400AN Sector 0a Sector 0b Sectors 1– 7 XC3S700AN Sector 0 0 Sector 0a Sector 0b Sectors 1– 15 XC3S1400AN Sector 0 0 Sector 0a Sector 0b Sectors 1– 15 Spartan-3AN FPGA In-System Flash User Guide UG333 (v2 ...
Page 60
... Chapter 5: Erase Commands Table 5-11: XC3S50AN, XC3S200AN, XC3S400AN Sector Boundaries Spartan-3AN FPGA XC3S50AN Pages per Sector 128 Addressing Default 264 Sector / Size Page 0a 0 0x00_0000 0x00_1000 1 128 0x01_0000 2 256 0x02_0000 3 384 0x03_0000 4 — — 5 — — 6 — — 7 — — Table 5-12: XC3S700AN, XC3S1400AN Sector Boundaries ...
Page 61
... Information Read Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 Table 5-13 and specified in the READY/BUSY bit (bit 7) of the Description FPGA Sector Erase Time XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN www.xilinx.com Sector Erase Spartan-3AN FPGA data Status Register indicates ...
Page 62
Chapter 5: Erase Commands 62 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
Page 63
... JEDEC-compatible device information ISF Memory Size 0011 = 1 Mbit: XC3S50AN 0111 = 4 Mbit: XC3S200AN or XC3S400AN 1001 = 8 Mbit: XC3S700AN 1011 = 16 Mbit: XC3S1400AN Table 6-1, the Status Register describes… Page to Buffer Compare (Program Verify) ...
Page 64
Chapter 6: Status and Information Commands READY/BUSY READY/BUSY status of the In-System Flash (ISF) memory is indicated by bit 7 in the Status Register, as defined in Table 6-2: READY/BUSY READY/BUSY 0 1 There are several commands that cause a ...
Page 65
... All programming and erase commands are prevented to ISF memory locations within the Sectors defined in the Sector Lockdown Register Read www.xilinx.com Status Register Description command matches the data stored in Page to Buffer Bits and 2) Associated FPGA(s) 1 Mbit XC3S50AN XC3S200AN 4 Mbit XC3S400AN 8 Mbit XC3S700AN 16 Mbit XC3S1400AN Bit 1) Description Sector Protection Register ...
Page 66
... Status Register value. www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide Table 6-6. FPGA Page Size XC3S50AN XC3S200AN 264 XC3S400AN XC3S700AN XC3S1400AN 528 XC3S50AN XC3S200AN 256 XC3S400AN XC3S700AN XC3S1400AN 512 at any time, including during any Read Status Byte ... Byte n XX ... XX Most-recent ... ...
Page 67
R See also Figure 1-3, page 12 Information Read The ISF memory supports JEDEC standards to enable systems and software to electronically query and identify the device while system. The ISF Information Read command complies with the ...
Page 68
... ISF memory is 0x1F. This value is different than the JEDEC code for Xilinx, which is 0x49. The Spartan-3AN FPGA product identifier is available via JTAG. Table 6-10: First Byte: Manufacturer Identifier FPGA All 68 Table Spartan-3AN FPGA XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Table JEDEC Assigned Code (0x1F) 7 ...
Page 69
... The three-bit Family Code is set to binary 001. • The five-bit Memory Density Code indicates the size of ISF memory array and differs between various FPGA densities, as shown in Status Register density code, shown in Table 6-11: Second Byte: Device Identifier (Part FPGA XC3S50AN (1 Mbit) XC3S200AN (4 Mbit) XC3S400AN (4 Mbit) XC3S700AN ...
Page 70
Chapter 6: Status and Information Commands 70 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
Page 71
R Power Management The Spartan V power rail to the Spartan-3AN FPGA. Note that write commands are not allowed CCAUX until 20 ms after VCCAUX has reached at least 2.5V. In general the ISF adds no significant current to the ...
Page 72
Chapter 7: Power Management CSB Figure 7-1: ISF Memory Enters Standby Mode when CSB is High Longer than 35 μs Thermal Considerations The ISF memory has negligible effect on the thermal considerations for the FPGA. The junction temperature of the ...
Page 73
R Sector-Based Program/Erase Protection The Spartan protect stored data against accidental or intentional changes. • The Sector Protection individual ISF memory sectors. • The Sector Lockdown essentially converting the Flash memory into read-only ROM. Once a sector is locked down, ...
Page 74
Chapter 8: Sector-Based Program/Erase Protection Sector Protection Using Sector Protection, the FPGA application protects selected memory sectors against erroneous program and erase cycles. There are five commands associated with the Sector Protection feature, as summarized in Table 8-2: Sector Protection ...
Page 75
... R Table 8-3: Sector Protection Register (one control byte per sector) XC3S50AN ◆ ◆ ◆ ◆ N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Table 8-4: Sector 0a and Sector 0b Protection Settings (Byte 0 in Sector Function Sectors 0a and 0b unprotected ...
Page 76
... Sector Table 8-6 Sector Protection Register Value (byte locations corresponds to sector) XC3S700AN, XC3S1400AN (16 bytes) XC3S200AN, XC3S400AN (8 bytes) XC3S50AN (4 bytes) Byte 4 Byte 5 Byte 6 Byte 7 Sector 0 Sector 1 Sector 2 0xFC programming data on the MOSI pin ...
Page 77
... If the FPGA application writes more than required number of bytes to the Sector Protection Register, then the data wraps back around to the beginning of the register. For example, if the application writes five bytes to the XC3S50AN, then the fifth byte actually overwrites the value for Sector 0. for information on how to protect or unprotect Sector 0 75. ...
Page 78
... The first data byte corresponds to Sector 0, the second data byte to Sector 1, and so on. The XC3S50AN FPGA provides four bytes. The XC3S200AN and the XC3S400AN FPGAs each provide 8 bytes. The XC3S700AN and XC3S1400AN FPGAs provide 16 bytes. If the FPGA application reads more than required number of bytes from the Sector Protection Register, any additional data provided on the MISO pin is undefined ...
Page 79
R Sector Protection Enable The Sector Protection Enable command applies the protection level specified in the Protection application must perform the following actions using the SPI_ACCESS design primitive. • Drive CSB Low while CLK is High or on the rising ...
Page 80
Chapter 8: Sector-Based Program/Erase Protection There are two commands associated with the Sector Lockdown feature, as shown in Table 8-10. Table 8-10: Sector Lockdown Commands Command Sector Lockdown Register Read Sector Lockdown Program Sector Lockdown Program To lock down a ...
Page 81
... The byte-level description for the Sector 0 status appears in The Lockdown Status for a specific sector is updated based on a command. The Sector Lockdown Register is a read-only location and cannot be directly modified. Table 8-12: Sector Lockdown Register (Read-Only) XC3S50AN ◆ ◆ ◆ ◆ N/A ...
Page 82
... The first data byte corresponds to Sector 0, the second data byte to Sector 1, and so on. The XC3S50AN FPGA provides four bytes. The XC3S200AN and the XC3S400AN FPGAs each provide 8 bytes. The XC3S700AN and the XC3S1400AN FPGAs provide 16 bytes. If the FPGA application reads more than required number of bytes from the Sector Lockdown Register, any additional data provided on the MISO pin is undefined ...
Page 83
R Security Register The Spartan Security Register, shown in Security Register The 128 bytes are further divided into two subfields. • The User-Defined Field (byte locations 0 through 63), can be programmed with any value at any time, but it ...
Page 84
Chapter 9: Security Register To issue the Security Register Program command sequence, the FPGA application must perform the following actions using the SPI_ACCESS design primitive. • Drive CSB Low while CLK is High or on the rising edge of CLK. ...
Page 85
R Security Register Read To read the using the SPI_ACCESS design primitive. • Drive CSB Low while CLK is High or on the rising edge of CLK. • On the falling edge of CLK, serially clock in the four-byte Security ...
Page 86
Chapter 9: Security Register 86 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
Page 87
... Power-of-2 addressing mode. The ISF memory must be erased and re- written after changing to the optional power-of-2 addressing mode. Table A-1 illustrates how the addressing mode affects total memory size. Table A-1: Default Addressing Mode vs. Power-of-2 Addressing Mode FPGA XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN How to Determine the Current Addressing Mode ...
Page 88
Appendix A: Optional Power-of-2 Addressing Mode Permanently Changing to the Power-of-2 Addressing Mode To permanently change over from the 2 addressing mode, the programmer or FPGA application must perform the following steps. • Drive CSB Low while CLK is High, ...
Page 89
R Power-of-2 Addressing Table A-3 summarizes the address mapping for the optional power-of-2 addressing mode. Table A-3: Power-of-2 Addressing Mode FPGA Binary Address 3S50AN 3S200AN 3S400AN 3S700AN 3S1400AN Binary Address Power-of-2 Page Addressing Table A-4 summarizes how page addresses are ...
Page 90
... Power-of-2 addressing mode. Sector 0 is subdivided into two subsectors, designated as Sector 0a and Sector 0b. These subsectors require additional address bits. Table A-6: Sector Addressing, Power-of-2 Addressing Mode FPGA / Sector 23 22 Binary Address 0 0 XC3S50AN Sector 0 0 Sector 0a Sector 0b Sectors 1– 3 XC3S200AN Sector 0 ...