XC3S50AN-5FTG256C Xilinx Inc, XC3S50AN-5FTG256C Datasheet - Page 46

• Manufacturer Part Number: XC3S50AN-5FTG256C
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-5FTG256C

• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Total Ram Bits: 55296
• Number Of I /o: 195
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Write and Program Commands
Page to Buffer Compare (Program Verify)
46
The Page to Buffer Compare command is not actually a programming command, but is
primarily used to verify correct programming of nonvolatile data in an ISF memory page.
As shown in
page against the contents of the designated SRAM page buffer. If one or more bits differ
between the page and buffer, then the
To issue a Page to Buffer Compare command, the FPGA application must perform the
following actions.
•
•
Table 4-7: Page to Buffer Compare Command Summary
Notes:
1. The Buffer 2 command is not available in the XC3S50AN because it has only one SRAM page buffer.
2. The Page to Buffer Compare command is supported in simulation.
MOSI
Pin
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the appropriate command code, shown in
Table
Page to Buffer 1 Compare
MOSI
MISO
Page to Buffer 2 Compare
CSB
CLK
Page to Buffer 2 Compare
4-2, most-significant bit first.
Page to Buffer 1 Compare
Figure
SPI_ACCESS
Command
Byte 1
Figure 4-4: Page to Buffer Compare Command
0x60
0x61
4-4, this command compares the contents of the addressed memory
available on
Buffer 2 not
XC3S50AN
www.xilinx.com
(1)
(0x60)
(0x61)
Compare
Default Addressing:
See
Power-of-2 Addressing:
See
High Address
?
Table 5-3, page 53
Table A-4, page 89
=
Spartan-3AN FPGA In-System Flash User Guide
Byte 2
Compares addressed Page against
designated SRAM page buffer.
bit (bit 6 in the
COMPARE (bit 6)
Status Register
READY/BUSY (bit 7)
7
0 = Comparison in progress
1 = Comparison complete, result in
0 = Matches exactly
1 = One or more bits are different
Flash Memory Array
24-bit Page Address
6
COMPARE (Status Register bit 6)
T
COMP
Middle Address
5
Page address
UG333 (v2.1) January 15, 2009
4
Byte 3
= 400 μs
Status
3
2
Register) is ‘1’.
UG333_c4_04_082307
1
Low Address
0
Don’t Care
Byte 4
XX
R