PIC16LF1526-I/MR Microchip Technology, PIC16LF1526-I/MR Datasheet - Page 140

• Manufacturer Part Number: PIC16LF1526-I/MR
• Description: MCU PIC 14KB FLASH 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1526-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C
• Maximum Clock Frequency: 20 MHz
• Number Of Timers: ÿ6 x 8-bit, 3 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16(L)F1526/27
REGISTER 12-32: WPUG: WEAK PULL-UP PORTG REGISTER
TABLE 12-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
TABLE 12-18: SUMMARY OF CONFIGURATION WORD WITH PORTG
DS41458A-page 140
CONFIG1
Legend:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5
bit 4-0
Note 1:
ANSELG
LATG
PORTG
TRISG
WPUG
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘ 0 ’. Shaded cells are not used by
Name
Name
U-0
—
2:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTG.
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
PORTG.
Bits
13:8
7:0
Unimplemented: Read as ‘ 0 ’
WPUG5: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘ 0 ’
Bit 7
—
—
—
—
—
Bit -/7
U-0
CP
—
—
Bit 6
MCLRE
—
—
—
—
—
Bit -/6
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-1/1
WPUG5
WPUG5
TRISG5
Bit 5
RG5
Bit 13/5
FCMEN
PWRTE
—
—
TRISG4
U-0
ANSG4
LATG4
Preliminary
—
Bit 4
RG4
—
Bit 12/4
IESO
WDTE<1:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
TRISG3
ANSG3
LATG3
Bit 3
RG3
CLKOUTEN
U-0
—
—
Bit 11/3
ANSG2
TRISG2
LATG2
Bit 2
RG2
—
Bit 10/2
U-0
BOREN<1:0>
—
TRISG1
ANSG1
LATG1
FOSC<2:0>
Bit 1
RG1
 2011 Microchip Technology Inc.
—
Bit 9/1
U-0
—
TRISG0
LATG0
Bit 0
RG0
—
—
Bit 8/0
—
Register
on Page
U-0
Register
on Page
—
139
139
138
138
140
48
bit 0